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https://github.com/c64scene-ar/llvm-6502.git
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d7e12561a5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202024 91177308-0d34-0410-b5e6-96231b3b80d8
73 lines
2.2 KiB
C++
73 lines
2.2 KiB
C++
//===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides AArch64 specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_AARCH64MCTARGETDESC_H
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#define LLVM_AARCH64MCTARGETDESC_H
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#include "llvm/Support/DataTypes.h"
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namespace llvm {
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCObjectWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class StringRef;
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class Target;
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class raw_ostream;
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extern Target TheAArch64leTarget;
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extern Target TheAArch64beTarget;
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namespace AArch64_MC {
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MCSubtargetInfo *createAArch64MCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS);
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}
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MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &STI,
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MCContext &Ctx);
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MCObjectWriter *createAArch64ELFObjectWriter(raw_ostream &OS,
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uint8_t OSABI,
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bool IsLittleEndian);
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MCAsmBackend *createAArch64leAsmBackend(const Target &T,
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const MCRegisterInfo &MRI,
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StringRef TT, StringRef CPU);
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MCAsmBackend *createAArch64beAsmBackend(const Target &T,
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const MCRegisterInfo &MRI,
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StringRef TT, StringRef CPU);
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} // End llvm namespace
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// Defines symbolic names for AArch64 registers. This defines a mapping from
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// register name to register number.
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//
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#define GET_REGINFO_ENUM
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#include "AArch64GenRegisterInfo.inc"
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// Defines symbolic names for the AArch64 instructions.
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//
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#define GET_INSTRINFO_ENUM
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#include "AArch64GenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "AArch64GenSubtargetInfo.inc"
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#endif
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