Justin Holewinski 7536ecf291 [NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs ... This converter currently only handles global variables in address space 0. For these variables, they are promoted to address space 1 (global memory), and all uses are updated to point to the result of a cvta.global instruction on the new variable. The motivation for this is address space 0 global variables are illegal since we cannot declare variables in the generic address space. Instead, we place the variables in address space 1 and explicitly convert the pointer to address space 0. This is primarily intended to help new users who expect to be able to place global variables in the default address space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182254 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-20 12:13:32 +00:00
..
AArch64	More test coverage for addFrameMove.	2013-05-16 20:50:56 +00:00
ARM	PR15868 fix.	2013-05-20 08:01:34 +00:00
CPP
Generic
Hexagon	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
Inputs
MBlaze
Mips	[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).	2013-05-16 21:17:15 +00:00
MSP430	DAGCombiner: Simplify inverted bit tests	2013-05-08 06:44:42 +00:00
NVPTX	[NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs	2013-05-20 12:13:32 +00:00
PowerPC	Check InlineAsm clobbers in PPCCTRLoops	2013-05-18 09:20:39 +00:00
R600	R600: Lower int_load_input to copyFromReg instead of Register node	2013-05-17 16:51:06 +00:00
SI
SPARC	Also expand 64-bit bitcasts.	2013-05-20 01:01:43 +00:00
SystemZ	[SystemZ] Make use of SUBTRACT HALFWORD	2013-05-15 15:05:29 +00:00
Thumb
Thumb2	Fix ARM FastISel tests, as a first step to enabling ARM FastISel	2013-05-14 16:26:38 +00:00
X86	X86: Bad peephole interaction between adc, MOV32r0	2013-05-18 01:02:03 +00:00
XCore	[XCore] Fix handling of functions where only the LR is spilled.	2013-05-09 16:43:42 +00:00