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https://github.com/c64scene-ar/llvm-6502.git
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f191c80cd7
This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
3.3 KiB
C++
95 lines
3.3 KiB
C++
//===- IA64RegisterInfo.h - IA64 Register Information Impl ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Duraid Madina and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the IA64 implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef IA64REGISTERINFO_H
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#define IA64REGISTERINFO_H
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#include "llvm/Target/MRegisterInfo.h"
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#include "IA64GenRegisterInfo.h.inc"
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namespace llvm { class llvm::Type; }
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namespace llvm {
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class TargetInstrInfo;
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struct IA64RegisterInfo : public IA64GenRegisterInfo {
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const TargetInstrInfo &TII;
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IA64RegisterInfo(const TargetInstrInfo &tii);
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/// Code Generation virtual methods...
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const;
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void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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void copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const;
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned DestReg, const MachineInstr *Orig) const;
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const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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const TargetRegisterClass* const* getCalleeSavedRegClasses(
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const MachineFunction *MF = 0) const;
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BitVector getReservedRegs(const MachineFunction &MF) const;
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bool hasFP(const MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, RegScavenger *RS = NULL) const;
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void emitPrologue(MachineFunction &MF) const;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
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// Debug information queries.
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unsigned getRARegister() const;
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unsigned getFrameRegister(MachineFunction &MF) const;
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// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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int getDwarfRegNum(unsigned RegNum) const;
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};
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} // End llvm namespace
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#endif
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