Craig Topper 75485d6746 Add X86 RORX instruction ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8		2011-10-23 07:34:00 +00:00
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Analysis	Make SCEV's brute force analysis stronger in two ways. Firstly, we should be	2011-10-22 19:58:20 +00:00
Archive
AsmParser
Bitcode	Also update the EH with bitcode. I missed this earlier. Thanks to Duncan for pointing it out.	2011-10-05 07:04:14 +00:00
CodeGen	Make sure that the landing pads themselves have no PHI instructions in them.	2011-10-21 22:08:56 +00:00
DebugInfo
ExecutionEngine
Linker
MC
Object	Use LLVMBool for a function that logically returns a boolean value.	2011-10-21 20:35:58 +00:00
Support	Fix build on mingw-w64.	2011-10-21 09:38:50 +00:00
TableGen
Target	Add X86 RORX instruction	2011-10-23 07:34:00 +00:00
Transforms	The element insertion code in scalar replacement doesn't handle incorrect	2011-10-23 07:02:10 +00:00
VMCore	Refactor code from inlining and globalopt that checks whether a function definition is unused, and enhance it so it can tell that functions which are only used by a blockaddress are in fact dead. This probably doesn't happen much on most code, but the Linux kernel's _THIS_IP_ can trigger this issue with blockaddress. (GlobalDCE can also handle the given tescase, but we only run that at -O3.) Found while looking at PR11180.	2011-10-20 05:23:42 +00:00
CMakeLists.txt
Makefile