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7225e27b4c
directly care about the Value class (it is templated so that the key can be any arbitrary Value subclass), it is in fact concretely tied to the Value class through the ValueHandle's CallbackVH interface which relies on the key type being some Value subclass to establish the value handle chain. Ironically, the unittest is already in the right library. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202824 91177308-0d34-0410-b5e6-96231b3b80d8
634 lines
22 KiB
C++
634 lines
22 KiB
C++
//===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Defines an instruction selector for the AMDGPU target.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPUISelLowering.h" // For AMDGPUISD
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#include "AMDGPURegisterInfo.h"
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#include "R600InstrInfo.h"
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#include "SIISelLowering.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/ValueMap.h"
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#include "llvm/Support/Compiler.h"
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#include <list>
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#include <queue>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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/// AMDGPU specific code to select AMDGPU machine instructions for
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/// SelectionDAG operations.
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class AMDGPUDAGToDAGISel : public SelectionDAGISel {
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// Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
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// make the right decision when generating code for different targets.
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const AMDGPUSubtarget &Subtarget;
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public:
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AMDGPUDAGToDAGISel(TargetMachine &TM);
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virtual ~AMDGPUDAGToDAGISel();
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SDNode *Select(SDNode *N);
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virtual const char *getPassName() const;
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virtual void PostprocessISelDAG();
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private:
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inline SDValue getSmallIPtrImm(unsigned Imm);
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bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
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const R600InstrInfo *TII);
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bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
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bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
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// Complex pattern selectors
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bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
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bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
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bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
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SDValue SimplifyI24(SDValue &Op);
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bool SelectI24(SDValue Addr, SDValue &Op);
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bool SelectU24(SDValue Addr, SDValue &Op);
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static bool checkType(const Value *ptr, unsigned int addrspace);
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static bool isGlobalStore(const StoreSDNode *N);
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static bool isPrivateStore(const StoreSDNode *N);
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static bool isLocalStore(const StoreSDNode *N);
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static bool isRegionStore(const StoreSDNode *N);
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bool isCPLoad(const LoadSDNode *N) const;
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bool isConstantLoad(const LoadSDNode *N, int cbID) const;
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bool isGlobalLoad(const LoadSDNode *N) const;
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bool isParamLoad(const LoadSDNode *N) const;
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bool isPrivateLoad(const LoadSDNode *N) const;
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bool isLocalLoad(const LoadSDNode *N) const;
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bool isRegionLoad(const LoadSDNode *N) const;
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const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
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bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
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bool SelectGlobalValueVariableOffset(SDValue Addr,
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SDValue &BaseReg, SDValue& Offset);
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bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
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// Include the pieces autogenerated from the target description.
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#include "AMDGPUGenDAGISel.inc"
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};
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} // end anonymous namespace
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/// \brief This pass converts a legalized DAG into a AMDGPU-specific
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// DAG, ready for instruction scheduling.
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FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
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) {
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return new AMDGPUDAGToDAGISel(TM);
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}
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AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
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}
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AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
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}
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/// \brief Determine the register class for \p OpNo
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/// \returns The register class of the virtual register that will be used for
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/// the given operand number \OpNo or NULL if the register class cannot be
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/// determined.
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const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
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unsigned OpNo) const {
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if (!N->isMachineOpcode()) {
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return NULL;
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}
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switch (N->getMachineOpcode()) {
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default: {
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const MCInstrDesc &Desc = TM.getInstrInfo()->get(N->getMachineOpcode());
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unsigned OpIdx = Desc.getNumDefs() + OpNo;
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if (OpIdx >= Desc.getNumOperands())
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return NULL;
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int RegClass = Desc.OpInfo[OpIdx].RegClass;
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if (RegClass == -1) {
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return NULL;
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}
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return TM.getRegisterInfo()->getRegClass(RegClass);
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}
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case AMDGPU::REG_SEQUENCE: {
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const TargetRegisterClass *SuperRC = TM.getRegisterInfo()->getRegClass(
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cast<ConstantSDNode>(N->getOperand(0))->getZExtValue());
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unsigned SubRegIdx =
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dyn_cast<ConstantSDNode>(N->getOperand(OpNo + 1))->getZExtValue();
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return TM.getRegisterInfo()->getSubClassWithSubReg(SuperRC, SubRegIdx);
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}
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}
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}
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SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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bool AMDGPUDAGToDAGISel::SelectADDRParam(
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SDValue Addr, SDValue& R1, SDValue& R2) {
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if (Addr.getOpcode() == ISD::FrameIndex) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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R2 = CurDAG->getTargetConstant(0, MVT::i32);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i32);
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}
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} else if (Addr.getOpcode() == ISD::ADD) {
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i32);
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}
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return true;
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}
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bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress) {
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return false;
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}
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return SelectADDRParam(Addr, R1, R2);
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}
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bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress) {
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return false;
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}
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if (Addr.getOpcode() == ISD::FrameIndex) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
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R2 = CurDAG->getTargetConstant(0, MVT::i64);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i64);
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}
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} else if (Addr.getOpcode() == ISD::ADD) {
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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} else {
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R1 = Addr;
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R2 = CurDAG->getTargetConstant(0, MVT::i64);
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}
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return true;
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}
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SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
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unsigned int Opc = N->getOpcode();
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if (N->isMachineOpcode()) {
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N->setNodeId(-1);
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return NULL; // Already selected.
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}
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switch (Opc) {
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default: break;
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// We are selecting i64 ADD here instead of custom lower it during
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// DAG legalization, so we can fold some i64 ADDs used for address
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// calculation into the LOAD and STORE instructions.
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case ISD::ADD: {
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const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
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if (N->getValueType(0) != MVT::i64 ||
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ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
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break;
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SDLoc DL(N);
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
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SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
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SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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DL, MVT::i32, LHS, Sub0);
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SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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DL, MVT::i32, LHS, Sub1);
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SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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DL, MVT::i32, RHS, Sub0);
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SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
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DL, MVT::i32, RHS, Sub1);
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SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
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SmallVector<SDValue, 8> AddLoArgs;
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AddLoArgs.push_back(SDValue(Lo0, 0));
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AddLoArgs.push_back(SDValue(Lo1, 0));
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SDNode *AddLo = CurDAG->getMachineNode(AMDGPU::S_ADD_I32, DL,
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VTList, AddLoArgs);
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SDValue Carry = SDValue(AddLo, 1);
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SDNode *AddHi = CurDAG->getMachineNode(AMDGPU::S_ADDC_U32, DL,
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MVT::i32, SDValue(Hi0, 0),
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SDValue(Hi1, 0), Carry);
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SDValue Args[5] = {
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CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
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SDValue(AddLo,0),
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Sub0,
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SDValue(AddHi,0),
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Sub1,
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};
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return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args, 5);
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}
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case ISD::BUILD_VECTOR: {
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unsigned RegClassID;
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const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
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const AMDGPURegisterInfo *TRI =
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static_cast<const AMDGPURegisterInfo*>(TM.getRegisterInfo());
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const SIRegisterInfo *SIRI =
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static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
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EVT VT = N->getValueType(0);
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unsigned NumVectorElts = VT.getVectorNumElements();
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assert(VT.getVectorElementType().bitsEq(MVT::i32));
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if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
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bool UseVReg = true;
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for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
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U != E; ++U) {
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if (!U->isMachineOpcode()) {
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continue;
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}
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const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
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if (!RC) {
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continue;
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}
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if (SIRI->isSGPRClass(RC)) {
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UseVReg = false;
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}
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}
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switch(NumVectorElts) {
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case 1: RegClassID = UseVReg ? AMDGPU::VReg_32RegClassID :
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AMDGPU::SReg_32RegClassID;
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break;
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case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
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AMDGPU::SReg_64RegClassID;
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break;
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case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
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AMDGPU::SReg_128RegClassID;
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break;
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case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
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AMDGPU::SReg_256RegClassID;
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break;
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case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
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AMDGPU::SReg_512RegClassID;
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break;
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default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
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}
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} else {
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// BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
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// that adds a 128 bits reg copy when going through TwoAddressInstructions
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// pass. We want to avoid 128 bits copies as much as possible because they
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// can't be bundled by our scheduler.
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switch(NumVectorElts) {
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case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
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case 4: RegClassID = AMDGPU::R600_Reg128RegClassID; break;
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default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
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}
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}
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SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32);
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if (NumVectorElts == 1) {
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return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS,
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VT.getVectorElementType(),
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N->getOperand(0), RegClass);
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}
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assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
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"supported yet");
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// 16 = Max Num Vector Elements
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// 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
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// 1 = Vector Register Class
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SDValue RegSeqArgs[16 * 2 + 1];
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RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, MVT::i32);
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bool IsRegSeq = true;
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for (unsigned i = 0; i < N->getNumOperands(); i++) {
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// XXX: Why is this here?
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if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
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IsRegSeq = false;
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break;
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}
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RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
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RegSeqArgs[1 + (2 * i) + 1] =
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CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
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}
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if (!IsRegSeq)
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break;
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return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
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RegSeqArgs, 2 * N->getNumOperands() + 1);
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}
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case ISD::BUILD_PAIR: {
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SDValue RC, SubReg0, SubReg1;
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const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
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if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
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break;
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}
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if (N->getValueType(0) == MVT::i128) {
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RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
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SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
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SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
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} else if (N->getValueType(0) == MVT::i64) {
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RC = CurDAG->getTargetConstant(AMDGPU::VSrc_64RegClassID, MVT::i32);
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SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
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SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
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} else {
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llvm_unreachable("Unhandled value type for BUILD_PAIR");
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}
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const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
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N->getOperand(1), SubReg1 };
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return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
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SDLoc(N), N->getValueType(0), Ops);
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}
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case AMDGPUISD::REGISTER_LOAD: {
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const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
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if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
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break;
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SDValue Addr, Offset;
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SelectADDRIndirect(N->getOperand(1), Addr, Offset);
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const SDValue Ops[] = {
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Addr,
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Offset,
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CurDAG->getTargetConstant(0, MVT::i32),
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N->getOperand(0),
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};
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return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, SDLoc(N),
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CurDAG->getVTList(MVT::i32, MVT::i64, MVT::Other),
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Ops);
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}
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case AMDGPUISD::REGISTER_STORE: {
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const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
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if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
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break;
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SDValue Addr, Offset;
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SelectADDRIndirect(N->getOperand(2), Addr, Offset);
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const SDValue Ops[] = {
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N->getOperand(1),
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Addr,
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Offset,
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CurDAG->getTargetConstant(0, MVT::i32),
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N->getOperand(0),
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};
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return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, SDLoc(N),
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CurDAG->getVTList(MVT::Other),
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Ops);
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}
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}
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return SelectCode(N);
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}
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bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
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if (!ptr) {
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return false;
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}
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Type *ptrType = ptr->getType();
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return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
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}
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bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
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return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
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}
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bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
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return (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
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&& !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
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&& !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS));
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}
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bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
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return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
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}
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bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
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return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
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}
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bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
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if (CbId == -1) {
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return checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS);
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}
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return checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
|
|
if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) {
|
|
const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
|
|
if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
|
|
N->getMemoryVT().bitsLT(MVT::i32)) {
|
|
return true;
|
|
}
|
|
}
|
|
return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
|
|
return checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
|
|
return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
|
|
return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
|
|
MachineMemOperand *MMO = N->getMemOperand();
|
|
if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
|
|
if (MMO) {
|
|
const Value *V = MMO->getValue();
|
|
const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
|
|
if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
|
|
if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
|
|
// Check to make sure we are not a constant pool load or a constant load
|
|
// that is marked as a private load
|
|
if (isCPLoad(N) || isConstantLoad(N, -1)) {
|
|
return false;
|
|
}
|
|
}
|
|
if (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
|
|
&& !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
|
|
&& !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS)
|
|
&& !checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)
|
|
&& !checkType(N->getSrcValue(), AMDGPUAS::PARAM_D_ADDRESS)
|
|
&& !checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS)) {
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
const char *AMDGPUDAGToDAGISel::getPassName() const {
|
|
return "AMDGPU DAG->DAG Pattern Instruction Selection";
|
|
}
|
|
|
|
#ifdef DEBUGTMP
|
|
#undef INT64_C
|
|
#endif
|
|
#undef DEBUGTMP
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Complex Patterns
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
|
|
SDValue& IntPtr) {
|
|
if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
|
|
IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
|
|
SDValue& BaseReg, SDValue &Offset) {
|
|
if (!dyn_cast<ConstantSDNode>(Addr)) {
|
|
BaseReg = Addr;
|
|
Offset = CurDAG->getIntPtrConstant(0, true);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
ConstantSDNode * IMMOffset;
|
|
|
|
if (Addr.getOpcode() == ISD::ADD
|
|
&& (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
|
|
&& isInt<16>(IMMOffset->getZExtValue())) {
|
|
|
|
Base = Addr.getOperand(0);
|
|
Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
|
|
return true;
|
|
// If the pointer address is constant, we can move it to the offset field.
|
|
} else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
|
|
&& isInt<16>(IMMOffset->getZExtValue())) {
|
|
Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
|
|
SDLoc(CurDAG->getEntryNode()),
|
|
AMDGPU::ZERO, MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
// Default case, no offset
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
return true;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
|
|
SDValue &Offset) {
|
|
ConstantSDNode *C;
|
|
|
|
if ((C = dyn_cast<ConstantSDNode>(Addr))) {
|
|
Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
|
|
Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
|
|
} else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
|
|
(C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
|
|
Base = Addr.getOperand(0);
|
|
Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
|
|
} else {
|
|
Base = Addr;
|
|
Offset = CurDAG->getTargetConstant(0, MVT::i32);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
SDValue AMDGPUDAGToDAGISel::SimplifyI24(SDValue &Op) {
|
|
APInt Demanded = APInt(32, 0x00FFFFFF);
|
|
APInt KnownZero, KnownOne;
|
|
TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true);
|
|
const TargetLowering *TLI = getTargetLowering();
|
|
if (TLI->SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) {
|
|
CurDAG->ReplaceAllUsesWith(Op, TLO.New);
|
|
CurDAG->RepositionNode(Op.getNode(), TLO.New.getNode());
|
|
return SimplifyI24(TLO.New);
|
|
} else {
|
|
return Op;
|
|
}
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectI24(SDValue Op, SDValue &I24) {
|
|
|
|
assert(Op.getValueType() == MVT::i32);
|
|
|
|
if (CurDAG->ComputeNumSignBits(Op) == 9) {
|
|
I24 = SimplifyI24(Op);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool AMDGPUDAGToDAGISel::SelectU24(SDValue Op, SDValue &U24) {
|
|
APInt KnownZero;
|
|
APInt KnownOne;
|
|
CurDAG->ComputeMaskedBits(Op, KnownZero, KnownOne);
|
|
|
|
assert (Op.getValueType() == MVT::i32);
|
|
|
|
// ANY_EXTEND and EXTLOAD operations can only be done on types smaller than
|
|
// i32. These smaller types are legal to use with the i24 instructions.
|
|
if ((KnownZero & APInt(KnownZero.getBitWidth(), 0xFF000000)) == 0xFF000000 ||
|
|
Op.getOpcode() == ISD::ANY_EXTEND ||
|
|
ISD::isEXTLoad(Op.getNode())) {
|
|
U24 = SimplifyI24(Op);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
|
|
const AMDGPUTargetLowering& Lowering =
|
|
(*(const AMDGPUTargetLowering*)getTargetLowering());
|
|
bool IsModified = false;
|
|
do {
|
|
IsModified = false;
|
|
// Go over all selected nodes and try to fold them a bit more
|
|
for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
|
|
E = CurDAG->allnodes_end(); I != E; ++I) {
|
|
|
|
SDNode *Node = I;
|
|
|
|
MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
|
|
if (!MachineNode)
|
|
continue;
|
|
|
|
SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
|
|
if (ResNode != Node) {
|
|
ReplaceUses(Node, ResNode);
|
|
IsModified = true;
|
|
}
|
|
}
|
|
CurDAG->RemoveDeadNodes();
|
|
} while (IsModified);
|
|
}
|