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https://github.com/c64scene-ar/llvm-6502.git
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825b93b2df
Add target specific rules for combining vselect dag nodes into movss/movsd when possible. If the vector type of the vselect dag node in input is either MVT::v4i13 or MVT::v4f32, then try to fold according to rules: 1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B) 2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A) If the vector type of the vselect dag node in input is either MVT::v2i64 or MVT::v2f64 (and we have SSE2), then try to fold according to rules: 3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B) 4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199683 91177308-0d34-0410-b5e6-96231b3b80d8
105 lines
3.0 KiB
LLVM
105 lines
3.0 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; AVX128 tests:
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;CHECK-LABEL: vsel_float:
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;CHECK: vblendvps
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;CHECK: ret
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define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %v1, <4 x float> %v2
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ret <4 x float> %vsel
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}
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;CHECK-LABEL: vsel_i32:
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;CHECK: vblendvps
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;CHECK: ret
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define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> %v1, <4 x i32> %v2
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ret <4 x i32> %vsel
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}
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;CHECK-LABEL: vsel_double:
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;CHECK: vmovsd
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;CHECK: ret
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define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
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%vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %v1, <2 x double> %v2
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ret <2 x double> %vsel
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}
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;CHECK-LABEL: vsel_i64:
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;CHECK: vmovsd
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;CHECK: ret
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define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
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%vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v1, <2 x i64> %v2
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ret <2 x i64> %vsel
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}
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;CHECK-LABEL: vsel_i8:
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;CHECK: vpblendvb
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;CHECK: ret
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define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
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%vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2
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ret <16 x i8> %vsel
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}
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; AVX256 tests:
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;CHECK-LABEL: vsel_float8:
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;CHECK: vblendvps
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;CHECK: ret
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define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x float> %v1, <8 x float> %v2
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ret <8 x float> %vsel
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}
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;CHECK-LABEL: vsel_i328:
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;CHECK: vblendvps
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;CHECK: ret
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define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i32> %v1, <8 x i32> %v2
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ret <8 x i32> %vsel
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}
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;CHECK-LABEL: vsel_double8:
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;CHECK: vblendvpd
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;CHECK: ret
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define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x double> %v1, <8 x double> %v2
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ret <8 x double> %vsel
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}
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;CHECK-LABEL: vsel_i648:
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;CHECK: vblendvpd
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;CHECK: ret
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define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {
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%vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i64> %v1, <8 x i64> %v2
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ret <8 x i64> %vsel
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}
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;; TEST blend + compares
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; CHECK: testa
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define <2 x double> @testa(<2 x double> %x, <2 x double> %y) {
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; CHECK: vcmplepd
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; CHECK: vblendvpd
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%max_is_x = fcmp oge <2 x double> %x, %y
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%max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
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ret <2 x double> %max
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}
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; CHECK: testb
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define <2 x double> @testb(<2 x double> %x, <2 x double> %y) {
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; CHECK: vcmpnlepd
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; CHECK: vblendvpd
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%min_is_x = fcmp ult <2 x double> %x, %y
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%min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
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ret <2 x double> %min
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}
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