mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-18 10:08:34 +00:00
361a78756b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76044 91177308-0d34-0410-b5e6-96231b3b80d8
491 lines
19 KiB
TableGen
491 lines
19 KiB
TableGen
//===- SystemZRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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class SystemZReg<string n> : Register<n> {
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let Namespace = "SystemZ";
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}
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class SystemZRegWithSubregs<string n, list<Register> subregs>
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: RegisterWithSubRegs<n, subregs> {
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let Namespace = "SystemZ";
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}
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// We identify all our registers with a 4-bit ID, for consistency's sake.
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// GPR32 - Lower 32 bits of one of the 16 64-bit general-purpose registers
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class GPR32<bits<4> num, string n> : SystemZReg<n> {
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field bits<4> Num = num;
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}
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// GPR64 - One of the 16 64-bit general-purpose registers
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class GPR64<bits<4> num, string n, list<Register> subregs,
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list<Register> aliases = []>
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: SystemZRegWithSubregs<n, subregs> {
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field bits<4> Num = num;
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let Aliases = aliases;
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}
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// GPR128 - 8 even-odd register pairs
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class GPR128<bits<4> num, string n, list<Register> subregs,
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list<Register> aliases = []>
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: SystemZRegWithSubregs<n, subregs> {
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field bits<4> Num = num;
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let Aliases = aliases;
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}
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// FPRS - Lower 32 bits of one of the 16 64-bit floating-point registers
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class FPRS<bits<4> num, string n> : SystemZReg<n> {
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field bits<4> Num = num;
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}
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// FPRL - One of the 16 64-bit floating-point registers
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class FPRL<bits<4> num, string n, list<Register> subregs>
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: SystemZRegWithSubregs<n, subregs> {
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field bits<4> Num = num;
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}
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// General-purpose registers
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def R0W : GPR32< 0, "r0">, DwarfRegNum<[0]>;
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def R1W : GPR32< 1, "r1">, DwarfRegNum<[1]>;
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def R2W : GPR32< 2, "r2">, DwarfRegNum<[2]>;
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def R3W : GPR32< 3, "r3">, DwarfRegNum<[3]>;
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def R4W : GPR32< 4, "r4">, DwarfRegNum<[4]>;
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def R5W : GPR32< 5, "r5">, DwarfRegNum<[5]>;
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def R6W : GPR32< 6, "r6">, DwarfRegNum<[6]>;
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def R7W : GPR32< 7, "r7">, DwarfRegNum<[7]>;
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def R8W : GPR32< 8, "r8">, DwarfRegNum<[8]>;
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def R9W : GPR32< 9, "r9">, DwarfRegNum<[9]>;
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def R10W : GPR32<10, "r10">, DwarfRegNum<[10]>;
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def R11W : GPR32<11, "r11">, DwarfRegNum<[11]>;
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def R12W : GPR32<12, "r12">, DwarfRegNum<[12]>;
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def R13W : GPR32<13, "r13">, DwarfRegNum<[13]>;
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def R14W : GPR32<14, "r14">, DwarfRegNum<[14]>;
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def R15W : GPR32<15, "r15">, DwarfRegNum<[15]>;
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def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>;
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def R1D : GPR64< 1, "r1", [R1W]>, DwarfRegNum<[1]>;
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def R2D : GPR64< 2, "r2", [R2W]>, DwarfRegNum<[2]>;
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def R3D : GPR64< 3, "r3", [R3W]>, DwarfRegNum<[3]>;
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def R4D : GPR64< 4, "r4", [R4W]>, DwarfRegNum<[4]>;
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def R5D : GPR64< 5, "r5", [R5W]>, DwarfRegNum<[5]>;
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def R6D : GPR64< 6, "r6", [R6W]>, DwarfRegNum<[6]>;
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def R7D : GPR64< 7, "r7", [R7W]>, DwarfRegNum<[7]>;
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def R8D : GPR64< 8, "r8", [R8W]>, DwarfRegNum<[8]>;
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def R9D : GPR64< 9, "r9", [R9W]>, DwarfRegNum<[9]>;
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def R10D : GPR64<10, "r10", [R10W]>, DwarfRegNum<[10]>;
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def R11D : GPR64<11, "r11", [R11W]>, DwarfRegNum<[11]>;
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def R12D : GPR64<12, "r12", [R12W]>, DwarfRegNum<[12]>;
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def R13D : GPR64<13, "r13", [R13W]>, DwarfRegNum<[13]>;
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def R14D : GPR64<14, "r14", [R14W]>, DwarfRegNum<[14]>;
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def R15D : GPR64<15, "r15", [R15W]>, DwarfRegNum<[15]>;
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// Register pairs
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def R0P : GPR64< 0, "r0", [R0W, R1W], [R0D, R1D]>, DwarfRegNum<[0]>;
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def R2P : GPR64< 2, "r2", [R2W, R3W], [R2D, R3D]>, DwarfRegNum<[2]>;
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def R4P : GPR64< 4, "r4", [R4W, R5W], [R4D, R5D]>, DwarfRegNum<[4]>;
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def R6P : GPR64< 6, "r6", [R6W, R7W], [R6D, R7D]>, DwarfRegNum<[6]>;
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def R8P : GPR64< 8, "r8", [R8W, R9W], [R8D, R9D]>, DwarfRegNum<[8]>;
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def R10P : GPR64<10, "r10", [R10W, R11W], [R10D, R11D]>, DwarfRegNum<[10]>;
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def R12P : GPR64<12, "r12", [R12W, R13W], [R12D, R13D]>, DwarfRegNum<[12]>;
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def R14P : GPR64<14, "r14", [R14W, R15W], [R14D, R15D]>, DwarfRegNum<[14]>;
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def R0Q : GPR128< 0, "r0", [R0D, R1D], [R0P]>, DwarfRegNum<[0]>;
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def R2Q : GPR128< 2, "r2", [R2D, R3D], [R2P]>, DwarfRegNum<[2]>;
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def R4Q : GPR128< 4, "r4", [R4D, R5D], [R4P]>, DwarfRegNum<[4]>;
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def R6Q : GPR128< 6, "r6", [R6D, R7D], [R6P]>, DwarfRegNum<[6]>;
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def R8Q : GPR128< 8, "r8", [R8D, R9D], [R8P]>, DwarfRegNum<[8]>;
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def R10Q : GPR128<10, "r10", [R10D, R11D], [R10P]>, DwarfRegNum<[10]>;
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def R12Q : GPR128<12, "r12", [R12D, R13D], [R12P]>, DwarfRegNum<[12]>;
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def R14Q : GPR128<14, "r14", [R14D, R15D], [R14P]>, DwarfRegNum<[14]>;
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// Floating-point registers
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def F0S : FPRS< 0, "f0">, DwarfRegNum<[16]>;
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def F1S : FPRS< 1, "f1">, DwarfRegNum<[17]>;
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def F2S : FPRS< 2, "f2">, DwarfRegNum<[18]>;
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def F3S : FPRS< 3, "f3">, DwarfRegNum<[19]>;
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def F4S : FPRS< 4, "f4">, DwarfRegNum<[20]>;
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def F5S : FPRS< 5, "f5">, DwarfRegNum<[21]>;
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def F6S : FPRS< 6, "f6">, DwarfRegNum<[22]>;
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def F7S : FPRS< 7, "f7">, DwarfRegNum<[23]>;
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def F8S : FPRS< 8, "f8">, DwarfRegNum<[24]>;
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def F9S : FPRS< 9, "f9">, DwarfRegNum<[25]>;
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def F10S : FPRS<10, "f10">, DwarfRegNum<[26]>;
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def F11S : FPRS<11, "f11">, DwarfRegNum<[27]>;
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def F12S : FPRS<12, "f12">, DwarfRegNum<[28]>;
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def F13S : FPRS<13, "f13">, DwarfRegNum<[29]>;
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def F14S : FPRS<14, "f14">, DwarfRegNum<[30]>;
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def F15S : FPRS<15, "f15">, DwarfRegNum<[31]>;
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def F0L : FPRL< 0, "f0", [F0S]>, DwarfRegNum<[16]>;
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def F1L : FPRL< 1, "f1", [F1S]>, DwarfRegNum<[17]>;
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def F2L : FPRL< 2, "f2", [F2S]>, DwarfRegNum<[18]>;
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def F3L : FPRL< 3, "f3", [F3S]>, DwarfRegNum<[19]>;
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def F4L : FPRL< 4, "f4", [F4S]>, DwarfRegNum<[20]>;
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def F5L : FPRL< 5, "f5", [F5S]>, DwarfRegNum<[21]>;
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def F6L : FPRL< 6, "f6", [F6S]>, DwarfRegNum<[22]>;
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def F7L : FPRL< 7, "f7", [F7S]>, DwarfRegNum<[23]>;
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def F8L : FPRL< 8, "f8", [F8S]>, DwarfRegNum<[24]>;
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def F9L : FPRL< 9, "f9", [F9S]>, DwarfRegNum<[25]>;
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def F10L : FPRL<10, "f10", [F10S]>, DwarfRegNum<[26]>;
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def F11L : FPRL<11, "f11", [F11S]>, DwarfRegNum<[27]>;
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def F12L : FPRL<12, "f12", [F12S]>, DwarfRegNum<[28]>;
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def F13L : FPRL<13, "f13", [F13S]>, DwarfRegNum<[29]>;
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def F14L : FPRL<14, "f14", [F14S]>, DwarfRegNum<[30]>;
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def F15L : FPRL<15, "f15", [F15S]>, DwarfRegNum<[31]>;
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// Status register
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def PSW : SystemZReg<"psw">;
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def subreg_32bit : PatLeaf<(i32 1)>;
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def subreg_even32 : PatLeaf<(i32 1)>;
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def subreg_odd32 : PatLeaf<(i32 2)>;
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def subreg_even : PatLeaf<(i32 3)>;
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def subreg_odd : PatLeaf<(i32 4)>;
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def : SubRegSet<1, [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D,
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R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
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[R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W,
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R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
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def : SubRegSet<3, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
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[R0D, R2D, R4D, R6D, R8D, R10D, R12D, R14D]>;
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def : SubRegSet<4, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
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[R1D, R3D, R5D, R7D, R9D, R11D, R13D, R15D]>;
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def : SubRegSet<1, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
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[R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>;
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def : SubRegSet<2, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
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[R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
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def : SubRegSet<1, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
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[R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>;
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def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
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[R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
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/// Register classes
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def GR32 : RegisterClass<"SystemZ", [i32], 32,
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// Volatile registers
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[R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W,
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// Frame pointer, sometimes allocable
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R11W,
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// Volatile, but not allocable
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R14W, R15W]>
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{
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned SystemZ_REG32[] = {
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SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
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SystemZ::R5W, SystemZ::R0W, SystemZ::R12W, SystemZ::R11W,
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SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
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SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
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};
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static const unsigned SystemZ_REG32_nofp[] = {
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SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
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SystemZ::R5W, SystemZ::R0W, SystemZ::R12W, /* No R11W */
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SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
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SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
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};
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GR32Class::iterator
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GR32Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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if (RI->hasFP(MF))
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return SystemZ_REG32_nofp;
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else
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return SystemZ_REG32;
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}
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GR32Class::iterator
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GR32Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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if (RI->hasFP(MF))
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return SystemZ_REG32_nofp + (sizeof(SystemZ_REG32_nofp) / sizeof(unsigned));
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else
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return SystemZ_REG32 + (sizeof(SystemZ_REG32) / sizeof(unsigned));
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}
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}];
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}
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/// Registers used to generate address. Everything except R0.
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def ADDR32 : RegisterClass<"SystemZ", [i32], 32,
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// Volatile registers
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[R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W,
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// Frame pointer, sometimes allocable
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R11W,
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// Volatile, but not allocable
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R14W, R15W]>
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{
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned SystemZ_ADDR32[] = {
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SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
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SystemZ::R5W, /* No R0W */ SystemZ::R12W, SystemZ::R11W,
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SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
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SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
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};
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static const unsigned SystemZ_ADDR32_nofp[] = {
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SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
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SystemZ::R5W, /* No R0W */ SystemZ::R12W, /* No R11W */
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SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
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SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
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};
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ADDR32Class::iterator
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ADDR32Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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if (RI->hasFP(MF))
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return SystemZ_ADDR32_nofp;
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else
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return SystemZ_ADDR32;
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}
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ADDR32Class::iterator
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ADDR32Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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if (RI->hasFP(MF))
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return SystemZ_ADDR32_nofp + (sizeof(SystemZ_ADDR32_nofp) / sizeof(unsigned));
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else
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return SystemZ_ADDR32 + (sizeof(SystemZ_ADDR32) / sizeof(unsigned));
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}
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}];
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}
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def GR64 : RegisterClass<"SystemZ", [i64], 64,
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// Volatile registers
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[R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D,
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// Frame pointer, sometimes allocable
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R11D,
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// Volatile, but not allocable
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R14D, R15D]>
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{
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let SubRegClassList = [GR32];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned SystemZ_REG64[] = {
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SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
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SystemZ::R5D, SystemZ::R0D, SystemZ::R12D, SystemZ::R11D,
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SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
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SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
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};
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static const unsigned SystemZ_REG64_nofp[] = {
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SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
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SystemZ::R5D, SystemZ::R0D, SystemZ::R12D, /* No R11D */
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SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
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SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
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};
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GR64Class::iterator
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GR64Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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if (RI->hasFP(MF))
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return SystemZ_REG64_nofp;
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else
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return SystemZ_REG64;
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}
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GR64Class::iterator
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GR64Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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if (RI->hasFP(MF))
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return SystemZ_REG64_nofp + (sizeof(SystemZ_REG64_nofp) / sizeof(unsigned));
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else
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return SystemZ_REG64 + (sizeof(SystemZ_REG64) / sizeof(unsigned));
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}
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}];
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}
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def ADDR64 : RegisterClass<"SystemZ", [i64], 64,
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// Volatile registers
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[R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D,
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// Frame pointer, sometimes allocable
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R11D,
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// Volatile, but not allocable
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R14D, R15D]>
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{
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let SubRegClassList = [ADDR32];
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned SystemZ_ADDR64[] = {
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SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
|
|
SystemZ::R5D, /* No R0D */ SystemZ::R12D, SystemZ::R11D,
|
|
SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
|
|
SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
|
|
};
|
|
static const unsigned SystemZ_ADDR64_nofp[] = {
|
|
SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
|
|
SystemZ::R5D, /* No R0D */ SystemZ::R12D, /* No R11D */
|
|
SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
|
|
SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
|
|
};
|
|
ADDR64Class::iterator
|
|
ADDR64Class::allocation_order_begin(const MachineFunction &MF) const {
|
|
const TargetMachine &TM = MF.getTarget();
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
if (RI->hasFP(MF))
|
|
return SystemZ_ADDR64_nofp;
|
|
else
|
|
return SystemZ_ADDR64;
|
|
}
|
|
ADDR64Class::iterator
|
|
ADDR64Class::allocation_order_end(const MachineFunction &MF) const {
|
|
const TargetMachine &TM = MF.getTarget();
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
if (RI->hasFP(MF))
|
|
return SystemZ_ADDR64_nofp + (sizeof(SystemZ_ADDR64_nofp) / sizeof(unsigned));
|
|
else
|
|
return SystemZ_ADDR64 + (sizeof(SystemZ_ADDR64) / sizeof(unsigned));
|
|
}
|
|
}];
|
|
}
|
|
|
|
// Even-odd register pairs
|
|
def GR64P : RegisterClass<"SystemZ", [v2i32], 64,
|
|
[R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P]>
|
|
{
|
|
let SubRegClassList = [GR32, GR32];
|
|
let MethodProtos = [{
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
}];
|
|
let MethodBodies = [{
|
|
static const unsigned SystemZ_REG64P[] = {
|
|
SystemZ::R0P, SystemZ::R2P, SystemZ::R4P, SystemZ::R10P,
|
|
SystemZ::R8P, SystemZ::R6P };
|
|
static const unsigned SystemZ_REG64P_nofp[] = {
|
|
SystemZ::R0P, SystemZ::R2P, SystemZ::R4P, /* NO R10P */
|
|
SystemZ::R8P, SystemZ::R6P };
|
|
GR64PClass::iterator
|
|
GR64PClass::allocation_order_begin(const MachineFunction &MF) const {
|
|
const TargetMachine &TM = MF.getTarget();
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
if (RI->hasFP(MF))
|
|
return SystemZ_REG64P_nofp;
|
|
else
|
|
return SystemZ_REG64P;
|
|
}
|
|
GR64PClass::iterator
|
|
GR64PClass::allocation_order_end(const MachineFunction &MF) const {
|
|
const TargetMachine &TM = MF.getTarget();
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
if (RI->hasFP(MF))
|
|
return SystemZ_REG64P_nofp + (sizeof(SystemZ_REG64P_nofp) / sizeof(unsigned));
|
|
else
|
|
return SystemZ_REG64P + (sizeof(SystemZ_REG64P) / sizeof(unsigned));
|
|
}
|
|
}];
|
|
}
|
|
|
|
def GR128 : RegisterClass<"SystemZ", [v2i64], 128,
|
|
[R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q]>
|
|
{
|
|
let SubRegClassList = [GR32, GR32, GR64, GR64];
|
|
let MethodProtos = [{
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
}];
|
|
let MethodBodies = [{
|
|
static const unsigned SystemZ_REG128[] = {
|
|
SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R10Q,
|
|
SystemZ::R8Q, SystemZ::R6Q };
|
|
static const unsigned SystemZ_REG128_nofp[] = {
|
|
SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, /* NO R10Q */
|
|
SystemZ::R8Q, SystemZ::R6Q };
|
|
GR128Class::iterator
|
|
GR128Class::allocation_order_begin(const MachineFunction &MF) const {
|
|
const TargetMachine &TM = MF.getTarget();
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
if (RI->hasFP(MF))
|
|
return SystemZ_REG128_nofp;
|
|
else
|
|
return SystemZ_REG128;
|
|
}
|
|
GR128Class::iterator
|
|
GR128Class::allocation_order_end(const MachineFunction &MF) const {
|
|
const TargetMachine &TM = MF.getTarget();
|
|
const TargetRegisterInfo *RI = TM.getRegisterInfo();
|
|
if (RI->hasFP(MF))
|
|
return SystemZ_REG128_nofp + (sizeof(SystemZ_REG128_nofp) / sizeof(unsigned));
|
|
else
|
|
return SystemZ_REG128 + (sizeof(SystemZ_REG128) / sizeof(unsigned));
|
|
}
|
|
}];
|
|
}
|
|
|
|
def FP32 : RegisterClass<"SystemZ", [f32], 32,
|
|
[F0S, F1S, F2S, F3S, F4S, F5S, F6S, F7S,
|
|
F8S, F9S, F10S, F11S, F12S, F13S, F14S, F15S]> {
|
|
let MethodProtos = [{
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
}];
|
|
let MethodBodies = [{
|
|
static const unsigned SystemZ_REGFP32[] = {
|
|
SystemZ::F0S, SystemZ::F2S, SystemZ::F4S, SystemZ::F6S,
|
|
SystemZ::F1S, SystemZ::F3S, SystemZ::F5S, SystemZ::F7S,
|
|
SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
|
|
SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
|
|
FP32Class::iterator
|
|
FP32Class::allocation_order_begin(const MachineFunction &MF) const {
|
|
return SystemZ_REGFP32;
|
|
}
|
|
FP32Class::iterator
|
|
FP32Class::allocation_order_end(const MachineFunction &MF) const {
|
|
return SystemZ_REGFP32 + (sizeof(SystemZ_REGFP32) / sizeof(unsigned));
|
|
}
|
|
}];
|
|
}
|
|
|
|
def FP64 : RegisterClass<"SystemZ", [f64], 64,
|
|
[F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L,
|
|
F8L, F9L, F10L, F11L, F12L, F13L, F14L, F15L]> {
|
|
let SubRegClassList = [FP32];
|
|
let MethodProtos = [{
|
|
iterator allocation_order_begin(const MachineFunction &MF) const;
|
|
iterator allocation_order_end(const MachineFunction &MF) const;
|
|
}];
|
|
let MethodBodies = [{
|
|
static const unsigned SystemZ_REGFP64[] = {
|
|
SystemZ::F0L, SystemZ::F2L, SystemZ::F4L, SystemZ::F6L,
|
|
SystemZ::F1L, SystemZ::F3L, SystemZ::F5L, SystemZ::F7L,
|
|
SystemZ::F8L, SystemZ::F9L, SystemZ::F10L, SystemZ::F11L,
|
|
SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L };
|
|
FP64Class::iterator
|
|
FP64Class::allocation_order_begin(const MachineFunction &MF) const {
|
|
return SystemZ_REGFP64;
|
|
}
|
|
FP64Class::iterator
|
|
FP64Class::allocation_order_end(const MachineFunction &MF) const {
|
|
return SystemZ_REGFP64 + (sizeof(SystemZ_REGFP64) / sizeof(unsigned));
|
|
}
|
|
}];
|
|
}
|
|
|
|
// Status flags registers.
|
|
def CCR : RegisterClass<"SystemZ", [i64], 64, [PSW]> {
|
|
let CopyCost = -1; // Don't allow copying of status registers.
|
|
}
|