mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-10 22:55:57 +00:00
d1303d2a66
A partial redefine needs to be treated like a tied operand, and the register must be reloaded while processing use operands. This fixes a bug where partially redefined registers were processed as normal defs with a reload added. The reload could clobber another use operand if it was a kill that allowed register reuse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107193 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
841 B
LLVM
23 lines
841 B
LLVM
; RUN: llc < %s -O0 -mcpu=cortex-a8 | FileCheck %s
|
|
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
|
|
target triple = "thumbv7-apple-darwin10"
|
|
|
|
; This tests the fast register allocator's handling of partial redefines:
|
|
;
|
|
; %reg1026<def> = VMOVv16i8 0, pred:14, pred:%reg0
|
|
; %reg1028:dsub_1<def> = EXTRACT_SUBREG %reg1026<kill>, 1
|
|
;
|
|
; %reg1026 gets allocated %Q0, and if %reg1028 is reloaded for the partial redef,
|
|
; it cannot also get %Q0.
|
|
|
|
; CHECK: vmov.i8 q0, #0x0
|
|
; CHECK-NOT: vld1.64 {d0,d1}
|
|
; CHECK: vmov.f64 d3, d0
|
|
|
|
define i32 @main(i32 %argc, i8** %argv) nounwind {
|
|
entry:
|
|
%0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 2> ; <<2 x i64>> [#uses=1]
|
|
store <2 x i64> %0, <2 x i64>* undef, align 16
|
|
ret i32 undef
|
|
}
|