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Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208690 91177308-0d34-0410-b5e6-96231b3b80d8
222 lines
7.8 KiB
C++
222 lines
7.8 KiB
C++
//===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the Mips specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsMachineFunction.h"
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#include "Mips.h"
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips-subtarget"
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "MipsGenSubtargetInfo.inc"
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// FIXME: Maybe this should be on by default when Mips16 is specified
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//
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static cl::opt<bool> Mixed16_32(
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"mips-mixed-16-32",
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cl::init(false),
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cl::desc("Allow for a mixture of Mips16 "
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"and Mips32 code in a single source file"),
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cl::Hidden);
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static cl::opt<bool> Mips_Os16(
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"mips-os16",
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cl::init(false),
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cl::desc("Compile all functions that don' use "
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"floating point as Mips 16"),
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cl::Hidden);
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static cl::opt<bool>
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Mips16HardFloat("mips16-hard-float", cl::NotHidden,
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cl::desc("MIPS: mips16 hard float enable."),
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cl::init(false));
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static cl::opt<bool>
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Mips16ConstantIslands(
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"mips16-constant-islands", cl::NotHidden,
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cl::desc("MIPS: mips16 constant islands enable."),
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cl::init(true));
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/// Select the Mips CPU for the given triple and cpu name.
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/// FIXME: Merge with the copy in MipsMCTargetDesc.cpp
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static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) {
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if (CPU.empty() || CPU == "generic") {
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Triple TheTriple(TT);
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if (TheTriple.getArch() == Triple::mips ||
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TheTriple.getArch() == Triple::mipsel)
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CPU = "mips32";
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else
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CPU = "mips64";
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}
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return CPU;
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}
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void MipsSubtarget::anchor() { }
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MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, bool little,
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Reloc::Model _RM, MipsTargetMachine *_TM)
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: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
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MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
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IsFP64bit(false), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false),
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HasCnMips(false), IsLinux(true), HasMips3_32(false), HasMips3_32r2(false),
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HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
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InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
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InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
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AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
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RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT) {
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std::string CPUName = CPU;
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CPUName = selectMipsCPU(TT, CPUName);
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// Parse features string.
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ParseSubtargetFeatures(CPUName, FS);
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if (InMips16Mode && !TM->Options.UseSoftFloat) {
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// Hard float for mips16 means essentially to compile as soft float
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// but to use a runtime library for soft float that is written with
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// native mips32 floating point instructions (those runtime routines
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// run in mips32 hard float mode).
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TM->Options.UseSoftFloat = true;
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TM->Options.FloatABIType = FloatABI::Soft;
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InMips16HardFloat = true;
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}
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PreviousInMips16Mode = InMips16Mode;
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// Initialize scheduling itinerary for the specified CPU.
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InstrItins = getInstrItineraryForCPU(CPUName);
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// Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
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// MIPS-V. They have not been tested and currently exist for the integrated
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// assembler only.
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if (MipsArchVersion == Mips1)
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report_fatal_error("Code generation for MIPS-I is not implemented", false);
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if (MipsArchVersion == Mips2)
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report_fatal_error("Code generation for MIPS-II is not implemented", false);
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if (MipsArchVersion == Mips3)
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report_fatal_error("Code generation for MIPS-III is not implemented",
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false);
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if (MipsArchVersion == Mips5)
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report_fatal_error("Code generation for MIPS-V is not implemented", false);
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// Assert exactly one ABI was chosen.
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assert(MipsABI != UnknownABI);
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assert((((getFeatureBits() & Mips::FeatureO32) != 0) +
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((getFeatureBits() & Mips::FeatureEABI) != 0) +
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((getFeatureBits() & Mips::FeatureN32) != 0) +
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((getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
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// Check if Architecture and ABI are compatible.
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assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
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(isGP64bit() && (isABI_N32() || isABI_N64()))) &&
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"Invalid Arch & ABI pair.");
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if (hasMSA() && !isFP64bit())
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report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
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"See -mattr=+fp64.",
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false);
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if (hasMips32r6()) {
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StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
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assert(isFP64bit());
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assert(isNaN2008());
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if (hasDSP())
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report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
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}
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// Is the target system Linux ?
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if (TT.find("linux") == std::string::npos)
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IsLinux = false;
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// Set UseSmallSection.
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// TODO: Investigate the IsLinux check. I suspect it's really checking for
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// bare-metal.
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UseSmallSection = !IsLinux && (RM == Reloc::Static);
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}
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bool
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MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel,
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TargetSubtargetInfo::AntiDepBreakMode &Mode,
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RegClassVector &CriticalPathRCs) const {
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Mode = TargetSubtargetInfo::ANTIDEP_NONE;
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CriticalPathRCs.clear();
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CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
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: &Mips::GPR32RegClass);
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return OptLevel >= CodeGenOpt::Aggressive;
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}
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//FIXME: This logic for reseting the subtarget along with
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// the helper classes can probably be simplified but there are a lot of
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// cases so we will defer rewriting this to later.
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//
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void MipsSubtarget::resetSubtarget(MachineFunction *MF) {
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bool ChangeToMips16 = false, ChangeToNoMips16 = false;
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DEBUG(dbgs() << "resetSubtargetFeatures" << "\n");
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AttributeSet FnAttrs = MF->getFunction()->getAttributes();
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ChangeToMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
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"mips16");
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ChangeToNoMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
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"nomips16");
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assert (!(ChangeToMips16 & ChangeToNoMips16) &&
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"mips16 and nomips16 specified on the same function");
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if (ChangeToMips16) {
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if (PreviousInMips16Mode)
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return;
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OverrideMode = Mips16Override;
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PreviousInMips16Mode = true;
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TM->setHelperClassesMips16();
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return;
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} else if (ChangeToNoMips16) {
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if (!PreviousInMips16Mode)
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return;
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OverrideMode = NoMips16Override;
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PreviousInMips16Mode = false;
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TM->setHelperClassesMipsSE();
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return;
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} else {
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if (OverrideMode == NoOverride)
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return;
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OverrideMode = NoOverride;
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DEBUG(dbgs() << "back to default" << "\n");
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if (inMips16Mode() && !PreviousInMips16Mode) {
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TM->setHelperClassesMips16();
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PreviousInMips16Mode = true;
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} else if (!inMips16Mode() && PreviousInMips16Mode) {
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TM->setHelperClassesMipsSE();
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PreviousInMips16Mode = false;
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}
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return;
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}
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}
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bool MipsSubtarget::mipsSEUsesSoftFloat() const {
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return TM->Options.UseSoftFloat && !InMips16HardFloat;
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}
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bool MipsSubtarget::useConstantIslands() {
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DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
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return Mips16ConstantIslands;
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}
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