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https://github.com/c64scene-ar/llvm-6502.git
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0821c72f11
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191168 91177308-0d34-0410-b5e6-96231b3b80d8
234 lines
6.4 KiB
TableGen
234 lines
6.4 KiB
TableGen
//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
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: Instruction {
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field bits<32> Inst;
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let Namespace = "SP";
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bits<2> op;
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let Inst{31-30} = op; // Top two bits are the 'op' field
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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//===----------------------------------------------------------------------===//
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// Format #2 instruction classes in the Sparc
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//===----------------------------------------------------------------------===//
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// Format 2 instructions
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class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSP<outs, ins, asmstr, pattern> {
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bits<3> op2;
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bits<22> imm22;
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let op = 0; // op = 0
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let Inst{24-22} = op2;
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let Inst{21-0} = imm22;
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}
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// Specific F2 classes: SparcV8 manual, page 44
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//
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class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
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: F2<outs, ins, asmstr, pattern> {
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bits<5> rd;
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let op2 = op2Val;
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let Inst{29-25} = rd;
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}
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class F2_2<bits<3> op2Val, dag outs, dag ins, string asmstr,
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list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
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bits<4> cond;
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bit annul = 0; // currently unused
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let op2 = op2Val;
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let Inst{29} = annul;
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let Inst{28-25} = cond;
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}
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//===----------------------------------------------------------------------===//
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// Format #3 instruction classes in the Sparc
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//===----------------------------------------------------------------------===//
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class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSP<outs, ins, asmstr, pattern> {
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bits<5> rd;
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bits<6> op3;
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bits<5> rs1;
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let op{1} = 1; // Op = 2 or 3
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let Inst{29-25} = rd;
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let Inst{24-19} = op3;
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let Inst{18-14} = rs1;
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}
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// Specific F3 classes: SparcV8 manual, page 44
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//
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class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
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string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
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bits<8> asi = 0; // asi not currently used
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bits<5> rs2;
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let op = opVal;
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let op3 = op3val;
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let Inst{13} = 0; // i field = 0
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let Inst{12-5} = asi; // address space identifier
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let Inst{4-0} = rs2;
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}
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class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
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string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
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bits<13> simm13;
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let op = opVal;
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let op3 = op3val;
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let Inst{13} = 1; // i field = 1
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let Inst{12-0} = simm13;
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}
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// floating-point
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class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
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string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
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bits<5> rs2;
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let op = opVal;
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let op3 = op3val;
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let Inst{13-5} = opfval; // fp opcode
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let Inst{4-0} = rs2;
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}
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// floating-point unary operations.
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class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
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string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
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bits<5> rs2;
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let op = opVal;
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let op3 = op3val;
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let rs1 = 0;
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let Inst{13-5} = opfval; // fp opcode
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let Inst{4-0} = rs2;
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}
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// floating-point compares.
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class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
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string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
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bits<5> rs2;
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let op = opVal;
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let op3 = op3val;
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let rd = 0;
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let Inst{13-5} = opfval; // fp opcode
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let Inst{4-0} = rs2;
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}
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// Shift by register rs2.
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class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
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string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
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bit x = xVal; // 1 for 64-bit shifts.
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bits<5> rs2;
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let op = opVal;
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let op3 = op3val;
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let Inst{13} = 0; // i field = 0
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let Inst{12} = x; // extended registers.
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let Inst{4-0} = rs2;
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}
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// Shift by immediate.
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class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins,
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string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
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bit x = xVal; // 1 for 64-bit shifts.
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bits<6> shcnt; // shcnt32 / shcnt64.
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let op = opVal;
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let op3 = op3val;
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let Inst{13} = 1; // i field = 1
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let Inst{12} = x; // extended registers.
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let Inst{5-0} = shcnt;
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}
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// Define rr and ri shift instructions with patterns.
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multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
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ValueType VT, RegisterClass RC> {
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def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, IntRegs:$rs2),
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!strconcat(OpcStr, " $rs, $rs2, $rd"),
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[(set VT:$rd, (OpNode VT:$rs, i32:$rs2))]>;
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def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, i32imm:$shcnt),
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!strconcat(OpcStr, " $rs, $shcnt, $rd"),
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[(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>;
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}
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class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSP<outs, ins, asmstr, pattern> {
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bits<5> rd;
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let op = 2;
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let Inst{29-25} = rd;
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let Inst{24-19} = op3;
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}
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class F4_1<bits<6> op3, dag outs, dag ins,
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string asmstr, list<dag> pattern>
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: F4<op3, outs, ins, asmstr, pattern> {
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bits<3> cc;
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bits<4> cond;
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bits<5> rs2;
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let Inst{4-0} = rs2;
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let Inst{11} = cc{0};
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let Inst{12} = cc{1};
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let Inst{13} = 0;
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let Inst{17-14} = cond;
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let Inst{18} = cc{2};
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}
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class F4_2<bits<6> op3, dag outs, dag ins,
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string asmstr, list<dag> pattern>
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: F4<op3, outs, ins, asmstr, pattern> {
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bits<3> cc;
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bits<4> cond;
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bits<11> simm11;
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let Inst{10-0} = simm11;
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let Inst{11} = cc{0};
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let Inst{12} = cc{1};
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let Inst{13} = 1;
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let Inst{17-14} = cond;
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let Inst{18} = cc{2};
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}
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class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins,
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string asmstr, list<dag> pattern>
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: F4<op3, outs, ins, asmstr, pattern> {
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bits<4> cond;
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bits<3> opf_cc;
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bits<5> rs2;
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let Inst{18} = 0;
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let Inst{17-14} = cond;
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let Inst{13-11} = opf_cc;
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let Inst{10-5} = opf_low;
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let Inst{4-0} = rs2;
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}
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