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backing out following to get it back to green, so I can investigate in peace: svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113980 91177308-0d34-0410-b5e6-96231b3b80d8
59 lines
1.9 KiB
LLVM
59 lines
1.9 KiB
LLVM
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck -check-prefix=T2 %s
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%struct.Foo = type { i8* }
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define %struct.Foo* @_ZN3Foo7collectEj(%struct.Foo* %this, i32 %acc) nounwind readonly align 2 {
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entry:
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%scevgep = getelementptr %struct.Foo* %this, i32 1
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br label %tailrecurse
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tailrecurse: ; preds = %sw.bb, %entry
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%lsr.iv2 = phi %struct.Foo* [ %scevgep3, %sw.bb ], [ %scevgep, %entry ]
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%lsr.iv = phi i32 [ %lsr.iv.next, %sw.bb ], [ 1, %entry ]
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%acc.tr = phi i32 [ %or, %sw.bb ], [ %acc, %entry ]
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%lsr.iv24 = bitcast %struct.Foo* %lsr.iv2 to i8**
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%scevgep5 = getelementptr i8** %lsr.iv24, i32 -1
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%tmp2 = load i8** %scevgep5
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%0 = ptrtoint i8* %tmp2 to i32
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; CHECK: and lr, r12, #3
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; CHECK-NEXT: tst r12, #3
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; CHECK-NEXT: beq LBB0_4
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; T2: movs r5, #3
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; T2-NEXT: mov r6, r4
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; T2-NEXT: ands r6, r5
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; T2-NEXT: tst r4, r5
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; T2-NEXT: beq LBB0_5
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%and = and i32 %0, 3
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%tst = icmp eq i32 %and, 0
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br i1 %tst, label %sw.bb, label %tailrecurse.switch
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tailrecurse.switch: ; preds = %tailrecurse
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switch i32 %and, label %sw.epilog [
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i32 1, label %sw.bb
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i32 3, label %sw.bb6
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i32 2, label %sw.bb8
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]
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sw.bb: ; preds = %tailrecurse.switch, %tailrecurse
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%shl = shl i32 %acc.tr, 1
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%or = or i32 %and, %shl
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%lsr.iv.next = add i32 %lsr.iv, 1
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%scevgep3 = getelementptr %struct.Foo* %lsr.iv2, i32 1
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br label %tailrecurse
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sw.bb6: ; preds = %tailrecurse.switch
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ret %struct.Foo* %lsr.iv2
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sw.bb8: ; preds = %tailrecurse.switch
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%tmp1 = add i32 %acc.tr, %lsr.iv
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%add.ptr11 = getelementptr inbounds %struct.Foo* %this, i32 %tmp1
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ret %struct.Foo* %add.ptr11
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sw.epilog: ; preds = %tailrecurse.switch
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ret %struct.Foo* undef
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}
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