mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-17 18:31:04 +00:00
4a3cd42601
This adds new node types for each intrinsic.
For instance, for addv, we have AArch64ISD::UADDV, such that:
(v4i32 (uaddv ...))
is the same as
(v4i32 (scalar_to_vector (i32 (int_aarch64_neon_uaddv ...))))
that is,
(v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
(i32 (int_aarch64_neon_uaddv ...)), ssub)
In a combine, we transform all such across-vector-lanes intrinsics to:
(i32 (extract_vector_elt (uaddv ...), 0))
This has one big advantage: by making the extract_element explicit, we
enable the existing patterns for lane-aware instructions to fire.
This lets us avoid needlessly going through the GPRs. Consider:
uint32x4_t test_mul(uint32x4_t a, uint32x4_t b) {
return vmulq_n_u32(a, vaddvq_u32(b));
}
We now generate:
addv.4s s1, v1
mul.4s v0, v0, v1[0]
instead of the previous:
addv.4s s1, v1
fmov w8, s1
dup.4s v1, w8
mul.4s v0, v1, v0
rdar://20044838
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231840 91177308-0d34-0410-b5e6-96231b3b80d8
408 lines
12 KiB
LLVM
408 lines
12 KiB
LLVM
; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -asm-verbose=false -mcpu=cyclone | FileCheck %s
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define signext i8 @test_vaddv_s8(<8 x i8> %a1) {
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; CHECK-LABEL: test_vaddv_s8:
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; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a1)
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%0 = trunc i32 %vaddv.i to i8
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ret i8 %0
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}
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define <8 x i8> @test_vaddv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
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; CHECK-LABEL: test_vaddv_s8_used_by_laneop:
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; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a2)
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%1 = trunc i32 %0 to i8
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%2 = insertelement <8 x i8> %a1, i8 %1, i32 3
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ret <8 x i8> %2
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}
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define signext i16 @test_vaddv_s16(<4 x i16> %a1) {
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; CHECK-LABEL: test_vaddv_s16:
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; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a1)
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%0 = trunc i32 %vaddv.i to i16
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ret i16 %0
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}
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define <4 x i16> @test_vaddv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
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; CHECK-LABEL: test_vaddv_s16_used_by_laneop:
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; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a2)
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%1 = trunc i32 %0 to i16
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%2 = insertelement <4 x i16> %a1, i16 %1, i32 3
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ret <4 x i16> %2
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}
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define i32 @test_vaddv_s32(<2 x i32> %a1) {
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; CHECK-LABEL: test_vaddv_s32:
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; 2 x i32 is not supported by the ISA, thus, this is a special case
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; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a1)
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ret i32 %vaddv.i
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}
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define <2 x i32> @test_vaddv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
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; CHECK-LABEL: test_vaddv_s32_used_by_laneop:
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; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1
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; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a2)
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%1 = insertelement <2 x i32> %a1, i32 %0, i32 1
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ret <2 x i32> %1
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}
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define i64 @test_vaddv_s64(<2 x i64> %a1) {
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; CHECK-LABEL: test_vaddv_s64:
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; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0
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; CHECK-NEXT: fmov x0, [[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a1)
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ret i64 %vaddv.i
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}
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define <2 x i64> @test_vaddv_s64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) {
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; CHECK-LABEL: test_vaddv_s64_used_by_laneop:
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; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.d v0[1], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a2)
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%1 = insertelement <2 x i64> %a1, i64 %0, i64 1
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ret <2 x i64> %1
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}
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define zeroext i8 @test_vaddv_u8(<8 x i8> %a1) {
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; CHECK-LABEL: test_vaddv_u8:
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; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a1)
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%0 = trunc i32 %vaddv.i to i8
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ret i8 %0
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}
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define <8 x i8> @test_vaddv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) {
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; CHECK-LABEL: test_vaddv_u8_used_by_laneop:
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; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a2)
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%1 = trunc i32 %0 to i8
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%2 = insertelement <8 x i8> %a1, i8 %1, i32 3
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ret <8 x i8> %2
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}
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define i32 @test_vaddv_u8_masked(<8 x i8> %a1) {
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; CHECK-LABEL: test_vaddv_u8_masked:
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; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a1)
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%0 = and i32 %vaddv.i, 511 ; 0x1ff
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ret i32 %0
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}
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define zeroext i16 @test_vaddv_u16(<4 x i16> %a1) {
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; CHECK-LABEL: test_vaddv_u16:
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; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a1)
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%0 = trunc i32 %vaddv.i to i16
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ret i16 %0
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}
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define <4 x i16> @test_vaddv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) {
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; CHECK-LABEL: test_vaddv_u16_used_by_laneop:
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; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a2)
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%1 = trunc i32 %0 to i16
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%2 = insertelement <4 x i16> %a1, i16 %1, i32 3
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ret <4 x i16> %2
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}
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define i32 @test_vaddv_u16_masked(<4 x i16> %a1) {
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; CHECK-LABEL: test_vaddv_u16_masked:
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; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a1)
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%0 = and i32 %vaddv.i, 3276799 ; 0x31ffff
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ret i32 %0
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}
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define i32 @test_vaddv_u32(<2 x i32> %a1) {
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; CHECK-LABEL: test_vaddv_u32:
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; 2 x i32 is not supported by the ISA, thus, this is a special case
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; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> %a1)
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ret i32 %vaddv.i
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}
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define <2 x i32> @test_vaddv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) {
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; CHECK-LABEL: test_vaddv_u32_used_by_laneop:
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; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1
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; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> %a2)
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%1 = insertelement <2 x i32> %a1, i32 %0, i32 1
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ret <2 x i32> %1
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}
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define float @test_vaddv_f32(<2 x float> %a1) {
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; CHECK-LABEL: test_vaddv_f32:
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; CHECK: faddp.2s s0, v0
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call float @llvm.aarch64.neon.faddv.f32.v2f32(<2 x float> %a1)
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ret float %vaddv.i
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}
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define float @test_vaddv_v4f32(<4 x float> %a1) {
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; CHECK-LABEL: test_vaddv_v4f32:
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; CHECK: faddp.4s [[REGNUM:v[0-9]+]], v0, v0
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; CHECK: faddp.2s s0, [[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call float @llvm.aarch64.neon.faddv.f32.v4f32(<4 x float> %a1)
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ret float %vaddv.i
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}
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define double @test_vaddv_f64(<2 x double> %a1) {
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; CHECK-LABEL: test_vaddv_f64:
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; CHECK: faddp.2d d0, v0
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call double @llvm.aarch64.neon.faddv.f64.v2f64(<2 x double> %a1)
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ret double %vaddv.i
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}
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define i64 @test_vaddv_u64(<2 x i64> %a1) {
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; CHECK-LABEL: test_vaddv_u64:
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; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0
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; CHECK-NEXT: fmov x0, [[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a1)
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ret i64 %vaddv.i
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}
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define <2 x i64> @test_vaddv_u64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) {
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; CHECK-LABEL: test_vaddv_u64_used_by_laneop:
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; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.d v0[1], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a2)
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%1 = insertelement <2 x i64> %a1, i64 %0, i64 1
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ret <2 x i64> %1
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}
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define <1 x i64> @test_vaddv_u64_to_vec(<2 x i64> %a1) {
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; CHECK-LABEL: test_vaddv_u64_to_vec:
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; CHECK: addp.2d d0, v0
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; CHECK-NOT: fmov
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; CHECK-NOT: ins
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; CHECK: ret
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entry:
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%vaddv.i = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a1)
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%vec = insertelement <1 x i64> undef, i64 %vaddv.i, i32 0
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ret <1 x i64> %vec
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}
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define signext i8 @test_vaddvq_s8(<16 x i8> %a1) {
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; CHECK-LABEL: test_vaddvq_s8:
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; CHECK: addv.16b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.b w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a1)
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%0 = trunc i32 %vaddv.i to i8
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ret i8 %0
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}
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define <16 x i8> @test_vaddvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
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; CHECK-LABEL: test_vaddvq_s8_used_by_laneop:
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; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a2)
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%1 = trunc i32 %0 to i8
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%2 = insertelement <16 x i8> %a1, i8 %1, i32 3
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ret <16 x i8> %2
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}
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define signext i16 @test_vaddvq_s16(<8 x i16> %a1) {
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; CHECK-LABEL: test_vaddvq_s16:
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; CHECK: addv.8h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: smov.h w0, v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a1)
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%0 = trunc i32 %vaddv.i to i16
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ret i16 %0
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}
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define <8 x i16> @test_vaddvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
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; CHECK-LABEL: test_vaddvq_s16_used_by_laneop:
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; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a2)
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%1 = trunc i32 %0 to i16
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%2 = insertelement <8 x i16> %a1, i16 %1, i32 3
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ret <8 x i16> %2
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}
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define i32 @test_vaddvq_s32(<4 x i32> %a1) {
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; CHECK-LABEL: test_vaddvq_s32:
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; CHECK: addv.4s [[REGNUM:s[0-9]+]], v0
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; CHECK-NEXT: fmov w0, [[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a1)
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ret i32 %vaddv.i
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}
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define <4 x i32> @test_vaddvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
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; CHECK-LABEL: test_vaddvq_s32_used_by_laneop:
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; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a2)
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%1 = insertelement <4 x i32> %a1, i32 %0, i32 3
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ret <4 x i32> %1
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}
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define zeroext i8 @test_vaddvq_u8(<16 x i8> %a1) {
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; CHECK-LABEL: test_vaddvq_u8:
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; CHECK: addv.16b b[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
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entry:
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%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a1)
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%0 = trunc i32 %vaddv.i to i8
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ret i8 %0
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}
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define <16 x i8> @test_vaddvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) {
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; CHECK-LABEL: test_vaddvq_u8_used_by_laneop:
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; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1
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; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0]
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a2)
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%1 = trunc i32 %0 to i8
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%2 = insertelement <16 x i8> %a1, i8 %1, i32 3
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ret <16 x i8> %2
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}
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define zeroext i16 @test_vaddvq_u16(<8 x i16> %a1) {
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; CHECK-LABEL: test_vaddvq_u16:
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; CHECK: addv.8h h[[REGNUM:[0-9]+]], v0
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; CHECK-NEXT: fmov w0, s[[REGNUM]]
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; CHECK-NEXT: ret
|
|
entry:
|
|
%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a1)
|
|
%0 = trunc i32 %vaddv.i to i16
|
|
ret i16 %0
|
|
}
|
|
|
|
define <8 x i16> @test_vaddvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) {
|
|
; CHECK-LABEL: test_vaddvq_u16_used_by_laneop:
|
|
; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1
|
|
; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0]
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a2)
|
|
%1 = trunc i32 %0 to i16
|
|
%2 = insertelement <8 x i16> %a1, i16 %1, i32 3
|
|
ret <8 x i16> %2
|
|
}
|
|
|
|
define i32 @test_vaddvq_u32(<4 x i32> %a1) {
|
|
; CHECK-LABEL: test_vaddvq_u32:
|
|
; CHECK: addv.4s [[REGNUM:s[0-9]+]], v0
|
|
; CHECK-NEXT: fmov [[FMOVRES:w[0-9]+]], [[REGNUM]]
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a1)
|
|
ret i32 %vaddv.i
|
|
}
|
|
|
|
define <4 x i32> @test_vaddvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) {
|
|
; CHECK-LABEL: test_vaddvq_u32_used_by_laneop:
|
|
; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1
|
|
; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0]
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a2)
|
|
%1 = insertelement <4 x i32> %a1, i32 %0, i32 3
|
|
ret <4 x i32> %1
|
|
}
|
|
|
|
declare i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32>)
|
|
|
|
declare i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16>)
|
|
|
|
declare i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8>)
|
|
|
|
declare i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32>)
|
|
|
|
declare i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16>)
|
|
|
|
declare i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8>)
|
|
|
|
declare i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64>)
|
|
|
|
declare i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32>)
|
|
|
|
declare i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16>)
|
|
|
|
declare i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8>)
|
|
|
|
declare i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32>)
|
|
|
|
declare i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64>)
|
|
|
|
declare i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16>)
|
|
|
|
declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>)
|
|
|
|
declare float @llvm.aarch64.neon.faddv.f32.v2f32(<2 x float> %a1)
|
|
declare float @llvm.aarch64.neon.faddv.f32.v4f32(<4 x float> %a1)
|
|
declare double @llvm.aarch64.neon.faddv.f64.v2f64(<2 x double> %a1)
|