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https://github.com/c64scene-ar/llvm-6502.git
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f95b162188
The SelectionDAGBuilder was promoting vector kernel arguments to legal types, but this won't work for R600 and SI since kernel arguments are stored in memory and can't be promoted. In order to handle vector arguments correctly we need to look at the original types from the LLVM IR function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193215 91177308-0d34-0410-b5e6-96231b3b80d8
195 lines
8.5 KiB
TableGen
195 lines
8.5 KiB
TableGen
//===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the SI registers
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//===----------------------------------------------------------------------===//
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class SIReg <string n, bits<16> encoding = 0> : Register<n> {
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let Namespace = "AMDGPU";
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let HWEncoding = encoding;
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}
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// Special Registers
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def VCC : SIReg<"VCC", 106>;
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def EXEC : SIReg<"EXEC", 126>;
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def SCC : SIReg<"SCC", 253>;
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def M0 : SIReg <"M0", 124>;
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// SGPR registers
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foreach Index = 0-101 in {
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def SGPR#Index : SIReg <"SGPR"#Index, Index>;
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}
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// VGPR registers
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foreach Index = 0-255 in {
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def VGPR#Index : SIReg <"VGPR"#Index, Index> {
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let HWEncoding{8} = 1;
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}
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}
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//===----------------------------------------------------------------------===//
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// Groupings using register classes and tuples
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//===----------------------------------------------------------------------===//
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// SGPR 32-bit registers
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def SGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
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(add (sequence "SGPR%u", 0, 101))>;
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// SGPR 64-bit registers
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def SGPR_64Regs : RegisterTuples<[sub0, sub1],
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[(add (decimate (trunc SGPR_32, 101), 2)),
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(add (decimate (shl SGPR_32, 1), 2))]>;
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// SGPR 128-bit registers
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def SGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
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[(add (decimate (trunc SGPR_32, 99), 4)),
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(add (decimate (shl SGPR_32, 1), 4)),
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(add (decimate (shl SGPR_32, 2), 4)),
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(add (decimate (shl SGPR_32, 3), 4))]>;
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// SGPR 256-bit registers
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def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
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[(add (decimate (trunc SGPR_32, 95), 4)),
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(add (decimate (shl SGPR_32, 1), 4)),
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(add (decimate (shl SGPR_32, 2), 4)),
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(add (decimate (shl SGPR_32, 3), 4)),
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(add (decimate (shl SGPR_32, 4), 4)),
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(add (decimate (shl SGPR_32, 5), 4)),
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(add (decimate (shl SGPR_32, 6), 4)),
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(add (decimate (shl SGPR_32, 7), 4))]>;
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// SGPR 512-bit registers
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def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
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sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
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[(add (decimate (trunc SGPR_32, 87), 4)),
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(add (decimate (shl SGPR_32, 1), 4)),
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(add (decimate (shl SGPR_32, 2), 4)),
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(add (decimate (shl SGPR_32, 3), 4)),
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(add (decimate (shl SGPR_32, 4), 4)),
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(add (decimate (shl SGPR_32, 5), 4)),
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(add (decimate (shl SGPR_32, 6), 4)),
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(add (decimate (shl SGPR_32, 7), 4)),
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(add (decimate (shl SGPR_32, 8), 4)),
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(add (decimate (shl SGPR_32, 9), 4)),
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(add (decimate (shl SGPR_32, 10), 4)),
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(add (decimate (shl SGPR_32, 11), 4)),
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(add (decimate (shl SGPR_32, 12), 4)),
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(add (decimate (shl SGPR_32, 13), 4)),
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(add (decimate (shl SGPR_32, 14), 4)),
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(add (decimate (shl SGPR_32, 15), 4))]>;
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// VGPR 32-bit registers
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def VGPR_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
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(add (sequence "VGPR%u", 0, 255))>;
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// VGPR 64-bit registers
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def VGPR_64 : RegisterTuples<[sub0, sub1],
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[(add (trunc VGPR_32, 255)),
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(add (shl VGPR_32, 1))]>;
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// VGPR 96-bit registers
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def VGPR_96 : RegisterTuples<[sub0, sub1, sub2],
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[(add (trunc VGPR_32, 254)),
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(add (shl VGPR_32, 1)),
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(add (shl VGPR_32, 2))]>;
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// VGPR 128-bit registers
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def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
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[(add (trunc VGPR_32, 253)),
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(add (shl VGPR_32, 1)),
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(add (shl VGPR_32, 2)),
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(add (shl VGPR_32, 3))]>;
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// VGPR 256-bit registers
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def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
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[(add (trunc VGPR_32, 249)),
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(add (shl VGPR_32, 1)),
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(add (shl VGPR_32, 2)),
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(add (shl VGPR_32, 3)),
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(add (shl VGPR_32, 4)),
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(add (shl VGPR_32, 5)),
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(add (shl VGPR_32, 6)),
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(add (shl VGPR_32, 7))]>;
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// VGPR 512-bit registers
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def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
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sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
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[(add (trunc VGPR_32, 241)),
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(add (shl VGPR_32, 1)),
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(add (shl VGPR_32, 2)),
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(add (shl VGPR_32, 3)),
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(add (shl VGPR_32, 4)),
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(add (shl VGPR_32, 5)),
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(add (shl VGPR_32, 6)),
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(add (shl VGPR_32, 7)),
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(add (shl VGPR_32, 8)),
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(add (shl VGPR_32, 9)),
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(add (shl VGPR_32, 10)),
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(add (shl VGPR_32, 11)),
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(add (shl VGPR_32, 12)),
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(add (shl VGPR_32, 13)),
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(add (shl VGPR_32, 14)),
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(add (shl VGPR_32, 15))]>;
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//===----------------------------------------------------------------------===//
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// Register classes used as source and destination
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//===----------------------------------------------------------------------===//
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// Special register classes for predicates and the M0 register
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def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)>;
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def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
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def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
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def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
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// Register class for all scalar registers (SGPRs + Special Registers)
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def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
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(add SGPR_32, M0Reg)
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>;
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def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64], 64, (add SGPR_64Regs)>;
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def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, i1], 64,
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(add SGPR_64Regs, VCCReg, EXECReg)
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>;
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def SReg_128 : RegisterClass<"AMDGPU", [i128, v4i32], 128, (add SGPR_128)>;
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def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
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def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 512, (add SGPR_512)>;
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// Register class for all vector registers (VGPRs + Interploation Registers)
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def VReg_32 : RegisterClass<"AMDGPU", [i32, f32, v1i32], 32, (add VGPR_32)>;
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def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 64, (add VGPR_64)>;
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def VReg_96 : RegisterClass<"AMDGPU", [untyped], 96, (add VGPR_96)> {
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let Size = 96;
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}
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def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, i128], 128, (add VGPR_128)>;
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def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>;
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def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
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//===----------------------------------------------------------------------===//
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// [SV]Src_* register classes, can have either an immediate or an register
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//===----------------------------------------------------------------------===//
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def SSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add SReg_32)>;
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def SSrc_64 : RegisterClass<"AMDGPU", [i64, f64, i1], 64, (add SReg_64)>;
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def VSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VReg_32, SReg_32)>;
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def VSrc_64 : RegisterClass<"AMDGPU", [i64, f64], 64, (add VReg_64, SReg_64)>;
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