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176194d4ee
This is a new algorithm that finds sets of register units that can be used to model registers pressure. This handles arbitrary, overlapping register classes. Each register class is associated with a (small) list of pressure sets. These are the dimensions of pressure affected by the register class's liveness. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154374 91177308-0d34-0410-b5e6-96231b3b80d8
65 lines
2.2 KiB
C++
65 lines
2.2 KiB
C++
//===- RegisterInfoEmitter.h - Generate a Register File Desc. ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting a description of a target
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// register file for a code generator. It uses instances of the Register,
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// RegisterAliases, and RegisterClass classes to gather this information.
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//
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//===----------------------------------------------------------------------===//
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#ifndef REGISTER_INFO_EMITTER_H
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#define REGISTER_INFO_EMITTER_H
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#include "llvm/TableGen/TableGenBackend.h"
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#include <vector>
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namespace llvm {
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class CodeGenRegBank;
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struct CodeGenRegister;
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class CodeGenTarget;
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class RegisterInfoEmitter : public TableGenBackend {
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RecordKeeper &Records;
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public:
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RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
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// runEnums - Print out enum values for all of the registers.
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void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
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// runMCDesc - Print out MC register descriptions.
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void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
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// runTargetHeader - Emit a header fragment for the register info emitter.
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void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
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CodeGenRegBank &Bank);
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// runTargetDesc - Output the target register and register file descriptions.
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void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
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CodeGenRegBank &Bank);
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// run - Output the register file description.
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void run(raw_ostream &o);
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private:
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void EmitRegMapping(raw_ostream &o,
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const std::vector<CodeGenRegister*> &Regs, bool isCtor);
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void EmitRegMappingTables(raw_ostream &o,
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const std::vector<CodeGenRegister*> &Regs,
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bool isCtor);
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void EmitRegClasses(raw_ostream &OS, CodeGenTarget &Target);
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void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
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const std::string &ClassName);
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};
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} // End llvm namespace
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#endif
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