Nate Begeman 6510b22cec Support multiple ValueTypes per RegisterClass, needed for upcoming vector ... work. This change has no effect on generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8		2005-12-01 04:51:06 +00:00
..
InstrSched	silence a warning	2005-10-02 16:27:59 +00:00
LiveVar
ModuloScheduling
RegAlloc	There is no need to build an archive version of this library	2005-10-24 02:09:03 +00:00
.cvsignore
DecomposeMultiDimRefs.cpp
EmitBytecodeToAssembly.cpp
InternalGlobalMapper.cpp
MachineCodeForInstruction.cpp
MachineCodeForInstruction.h
MachineFunctionInfo.cpp
MachineFunctionInfo.h
MachineInstrAnnot.h
Makefile
MappingInfo.cpp
MappingInfo.h
SparcV9_F2.td
SparcV9_F3.td
SparcV9_F4.td
SparcV9.burg.in
SparcV9.td
SparcV9AsmPrinter.cpp
SparcV9BurgISel.cpp
SparcV9BurgISel.h
SparcV9CodeEmitter.cpp
SparcV9CodeEmitter.h
SparcV9FrameInfo.cpp
SparcV9FrameInfo.h
SparcV9Instr.def
SparcV9InstrForest.h
SparcV9InstrInfo.h
SparcV9InstrInfo.td
SparcV9Internals.h
SparcV9JITInfo.cpp
SparcV9JITInfo.h
SparcV9PeepholeOpts.cpp
SparcV9PreSelection.cpp
SparcV9PrologEpilogInserter.cpp
SparcV9RegClassInfo.cpp
SparcV9RegClassInfo.h
SparcV9RegInfo.cpp
SparcV9RegInfo.h
SparcV9RegisterInfo.cpp	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
SparcV9RegisterInfo.h
SparcV9RegisterInfo.td	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
SparcV9Relocations.h
SparcV9SchedInfo.cpp
SparcV9StackSlots.cpp
SparcV9TargetMachine.cpp	Add a new option to indicate we want the code generator to emit code quickly,not spending tons of time microoptimizing it. This is useful for an -O0style of build.	2005-11-08 02:11:51 +00:00
SparcV9TargetMachine.h	Add a new option to indicate we want the code generator to emit code quickly,not spending tons of time microoptimizing it. This is useful for an -O0style of build.	2005-11-08 02:11:51 +00:00
SparcV9TmpInstr.cpp
SparcV9TmpInstr.h