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hasInFlag, hasOutFlag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25155 91177308-0d34-0410-b5e6-96231b3b80d8
194 lines
7.4 KiB
C++
194 lines
7.4 KiB
C++
//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SparcV8 implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8.h"
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#include "SparcV8RegisterInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/Type.h"
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#include "llvm/ADT/STLExtras.h"
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#include <iostream>
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using namespace llvm;
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SparcV8RegisterInfo::SparcV8RegisterInfo()
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: SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
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V8::ADJCALLSTACKUP) {}
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void SparcV8RegisterInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
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if (RC == V8::IntRegsRegisterClass)
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BuildMI (MBB, I, V8::STri, 3).addFrameIndex (FrameIdx).addSImm (0)
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.addReg (SrcReg);
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else if (RC == V8::FPRegsRegisterClass)
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BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
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.addReg (SrcReg);
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else if (RC == V8::DFPRegsRegisterClass)
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BuildMI (MBB, I, V8::STDFri, 3).addFrameIndex (FrameIdx).addSImm (0)
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.addReg (SrcReg);
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else
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assert (0 && "Can't store this register to stack slot");
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}
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void SparcV8RegisterInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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if (RC == V8::IntRegsRegisterClass)
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BuildMI (MBB, I, V8::LDri, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
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else if (RC == V8::FPRegsRegisterClass)
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BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
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.addSImm (0);
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else if (RC == V8::DFPRegsRegisterClass)
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BuildMI (MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex (FrameIdx)
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.addSImm (0);
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else
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assert(0 && "Can't load this register from stack slot");
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}
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void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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if (RC == V8::IntRegsRegisterClass)
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BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
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else if (RC == V8::FPRegsRegisterClass)
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BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
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else if (RC == V8::DFPRegsRegisterClass)
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BuildMI (MBB, I, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
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else
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assert (0 && "Can't copy this register");
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}
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void SparcV8RegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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MachineInstr &MI = *I;
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int Size = MI.getOperand(0).getImmedValue();
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if (MI.getOpcode() == V8::ADJCALLSTACKDOWN)
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Size = -Size;
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if (Size)
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BuildMI(MBB, I, V8::ADDri, 2, V8::O6).addReg(V8::O6).addSImm(Size);
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MBB.erase(I);
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}
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void
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SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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unsigned i = 0;
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MachineInstr &MI = *II;
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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// Addressable stack objects are accessed using neg. offsets from %fp
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MachineFunction &MF = *MI.getParent()->getParent();
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(i+1).getImmedValue();
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// Replace frame index with a frame pointer reference.
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if (Offset >= -4096 && Offset <= 4095) {
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// If the offset is small enough to fit in the immediate field, directly
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// encode it.
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MI.SetMachineOperandReg(i, V8::I6);
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MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,Offset);
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} else {
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// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
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// scavenge a register here instead of reserving G1 all of the time.
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unsigned OffHi = (unsigned)Offset >> 10U;
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BuildMI(*MI.getParent(), II, V8::SETHIi, 1, V8::G1).addImm(OffHi);
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// Emit G1 = G1 + I6
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BuildMI(*MI.getParent(), II, V8::ADDrr, 2,
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V8::G1).addReg(V8::G1).addReg(V8::I6);
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// Insert: G1+%lo(offset) into the user.
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MI.SetMachineOperandReg(i, V8::I1);
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MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,
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Offset & ((1 << 10)-1));
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}
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}
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void SparcV8RegisterInfo::
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processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
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void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Get the number of bytes to allocate from the FrameInfo
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int NumBytes = (int) MFI->getStackSize();
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// Emit the correct save instruction based on the number of bytes in
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// the frame. Minimum stack frame size according to V8 ABI is:
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// 16 words for register window spill
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// 1 word for address of returned aggregate-value
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// + 6 words for passing parameters on the stack
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// ----------
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// 23 words * 4 bytes per word = 92 bytes
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NumBytes += 92;
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// Round up to next doubleword boundary -- a double-word boundary
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// is required by the ABI.
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NumBytes = (NumBytes + 7) & ~7;
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NumBytes = -NumBytes;
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if (NumBytes >= -4096) {
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BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
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V8::O6).addImm(NumBytes).addReg(V8::O6);
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} else {
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MachineBasicBlock::iterator InsertPt = MBB.begin();
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// Emit this the hard way. This clobbers G1 which we always know is
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// available here.
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unsigned OffHi = (unsigned)NumBytes >> 10U;
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BuildMI(MBB, InsertPt, V8::SETHIi, 1, V8::G1).addImm(OffHi);
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// Emit G1 = G1 + I6
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BuildMI(MBB, InsertPt, V8::ORri, 2, V8::G1)
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.addReg(V8::G1).addImm(NumBytes & ((1 << 10)-1));
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BuildMI(MBB, InsertPt, V8::SAVErr, 2,
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V8::O6).addReg(V8::O6).addReg(V8::G1);
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}
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}
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void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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assert(MBBI->getOpcode() == V8::RETL &&
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"Can only put epilog before 'retl' instruction!");
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BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
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}
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#include "SparcV8GenRegisterInfo.inc"
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const TargetRegisterClass*
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SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
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switch (Ty->getTypeID()) {
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case Type::FloatTyID: return V8::FPRegsRegisterClass;
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case Type::DoubleTyID: return V8::DFPRegsRegisterClass;
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case Type::LongTyID:
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case Type::ULongTyID: assert(0 && "Long values do not fit in registers!");
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default: assert(0 && "Invalid type to getClass!");
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case Type::BoolTyID:
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case Type::SByteTyID:
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case Type::UByteTyID:
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case Type::ShortTyID:
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case Type::UShortTyID:
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case Type::IntTyID:
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case Type::UIntTyID:
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case Type::PointerTyID: return V8::IntRegsRegisterClass;
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}
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}
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