mirror of
https://github.com/c64scene-ar/llvm-6502.git
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fce288fc91
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
90 lines
2.9 KiB
LLVM
90 lines
2.9 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
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;CHECK: vduplane8:
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;CHECK: vdup.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
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;CHECK: vduplane16:
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;CHECK: vdup.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
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;CHECK: vduplane32:
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;CHECK: vdup.32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
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ret <2 x i32> %tmp2
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}
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define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
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;CHECK: vduplanefloat:
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;CHECK: vdup.32
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%tmp1 = load <2 x float>* %A
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
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ret <2 x float> %tmp2
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}
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define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
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;CHECK: vduplaneQ8:
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;CHECK: vdup.8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
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;CHECK: vduplaneQ16:
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;CHECK: vdup.16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
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;CHECK: vduplaneQ32:
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;CHECK: vdup.32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
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ret <4 x i32> %tmp2
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}
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define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
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;CHECK: vduplaneQfloat:
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;CHECK: vdup.32
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%tmp1 = load <2 x float>* %A
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%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
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ret <4 x float> %tmp2
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}
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define arm_apcscc <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone {
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entry:
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%0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
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ret <2 x i64> %0
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}
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define arm_apcscc <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone {
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entry:
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%0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
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ret <2 x i64> %0
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}
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define arm_apcscc <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone {
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entry:
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%0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 1, i32 1>
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ret <2 x double> %0
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}
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define arm_apcscc <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone {
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entry:
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%0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0>
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ret <2 x double> %0
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}
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