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d84ccfaf50
To add a frame now there is a dedicated addFrameMove which also takes care of constructing the move itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181657 91177308-0d34-0410-b5e6-96231b3b80d8
634 lines
25 KiB
C++
634 lines
25 KiB
C++
//===- AArch64FrameLowering.cpp - AArch64 Frame Information ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AArch64 implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64FrameLowering.h"
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#include "AArch64MachineFunctionInfo.h"
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#include "AArch64InstrInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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void AArch64FrameLowering::splitSPAdjustments(uint64_t Total,
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uint64_t &Initial,
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uint64_t &Residual) const {
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// 0x1f0 here is a pessimistic (i.e. realistic) boundary: x-register LDP
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// instructions have a 7-bit signed immediate scaled by 8, giving a reach of
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// 0x1f8, but stack adjustment should always be a multiple of 16.
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if (Total <= 0x1f0) {
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Initial = Total;
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Residual = 0;
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} else {
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Initial = 0x1f0;
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Residual = Total - Initial;
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}
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}
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void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const {
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AArch64MachineFunctionInfo *FuncInfo =
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MF.getInfo<AArch64MachineFunctionInfo>();
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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MachineModuleInfo &MMI = MF.getMMI();
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bool NeedsFrameMoves = MMI.hasDebugInfo()
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|| MF.getFunction()->needsUnwindTableEntry();
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uint64_t NumInitialBytes, NumResidualBytes;
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// Currently we expect the stack to be laid out by
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// sub sp, sp, #initial
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// stp x29, x30, [sp, #offset]
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// ...
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// str xxx, [sp, #offset]
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// sub sp, sp, #rest (possibly via extra instructions).
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if (MFI->getCalleeSavedInfo().size()) {
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// If there are callee-saved registers, we want to store them efficiently as
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// a block, and virtual base assignment happens too early to do it for us so
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// we adjust the stack in two phases: first just for callee-saved fiddling,
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// then to allocate the rest of the frame.
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splitSPAdjustments(MFI->getStackSize(), NumInitialBytes, NumResidualBytes);
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} else {
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// If there aren't any callee-saved registers, two-phase adjustment is
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// inefficient. It's more efficient to adjust with NumInitialBytes too
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// because when we're in a "callee pops argument space" situation, that pop
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// must be tacked onto Initial for correctness.
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NumInitialBytes = MFI->getStackSize();
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NumResidualBytes = 0;
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}
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// Tell everyone else how much adjustment we're expecting them to use. In
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// particular if an adjustment is required for a tail call the epilogue could
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// have a different view of things.
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FuncInfo->setInitialStackAdjust(NumInitialBytes);
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emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumInitialBytes,
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MachineInstr::FrameSetup);
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if (NeedsFrameMoves && NumInitialBytes) {
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// We emit this update even if the CFA is set from a frame pointer later so
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// that the CFA is valid in the interim.
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MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
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.addSym(SPLabel);
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MachineLocation Dst(MachineLocation::VirtualFP);
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MachineLocation Src(AArch64::XSP, NumInitialBytes);
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MMI.addFrameMove(SPLabel, Dst, Src);
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}
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// Otherwise we need to set the frame pointer and/or add a second stack
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// adjustment.
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bool FPNeedsSetting = hasFP(MF);
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for (; MBBI != MBB.end(); ++MBBI) {
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// Note that this search makes strong assumptions about the operation used
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// to store the frame-pointer: it must be "STP x29, x30, ...". This could
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// change in future, but until then there's no point in implementing
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// untestable more generic cases.
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if (FPNeedsSetting && MBBI->getOpcode() == AArch64::LSPair64_STR
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&& MBBI->getOperand(0).getReg() == AArch64::X29) {
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int64_t X29FrameIdx = MBBI->getOperand(2).getIndex();
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FuncInfo->setFramePointerOffset(MFI->getObjectOffset(X29FrameIdx));
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++MBBI;
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emitRegUpdate(MBB, MBBI, DL, TII, AArch64::X29, AArch64::XSP,
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AArch64::X29,
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NumInitialBytes + MFI->getObjectOffset(X29FrameIdx),
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MachineInstr::FrameSetup);
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// The offset adjustment used when emitting debugging locations relative
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// to whatever frame base is set. AArch64 uses the default frame base (FP
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// or SP) and this adjusts the calculations to be correct.
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MFI->setOffsetAdjustment(- MFI->getObjectOffset(X29FrameIdx)
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- MFI->getStackSize());
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if (NeedsFrameMoves) {
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MCSymbol *FPLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
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.addSym(FPLabel);
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MachineLocation Dst(MachineLocation::VirtualFP);
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MachineLocation Src(AArch64::X29, -MFI->getObjectOffset(X29FrameIdx));
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MMI.addFrameMove(FPLabel, Dst, Src);
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}
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FPNeedsSetting = false;
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}
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if (!MBBI->getFlag(MachineInstr::FrameSetup))
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break;
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}
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assert(!FPNeedsSetting && "Frame pointer couldn't be set");
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emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumResidualBytes,
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MachineInstr::FrameSetup);
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// Now we emit the rest of the frame setup information, if necessary: we've
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// already noted the FP and initial SP moves so we're left with the prologue's
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// final SP update and callee-saved register locations.
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if (!NeedsFrameMoves)
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return;
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// Reuse the label if appropriate, so create it in this outer scope.
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MCSymbol *CSLabel = 0;
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// The rest of the stack adjustment
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if (!hasFP(MF) && NumResidualBytes) {
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CSLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
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.addSym(CSLabel);
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MachineLocation Dst(MachineLocation::VirtualFP);
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MachineLocation Src(AArch64::XSP, NumResidualBytes + NumInitialBytes);
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MMI.addFrameMove(CSLabel, Dst, Src);
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}
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// And any callee-saved registers (it's fine to leave them to the end here,
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// because the old values are still valid at this point.
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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if (CSI.size()) {
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if (!CSLabel) {
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CSLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
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.addSym(CSLabel);
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}
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for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
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E = CSI.end(); I != E; ++I) {
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MachineLocation Dst(MachineLocation::VirtualFP,
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MFI->getObjectOffset(I->getFrameIdx()));
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MachineLocation Src(I->getReg());
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MMI.addFrameMove(CSLabel, Dst, Src);
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}
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}
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}
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void
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AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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AArch64MachineFunctionInfo *FuncInfo =
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MF.getInfo<AArch64MachineFunctionInfo>();
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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DebugLoc DL = MBBI->getDebugLoc();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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unsigned RetOpcode = MBBI->getOpcode();
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// Initial and residual are named for consitency with the prologue. Note that
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// in the epilogue, the residual adjustment is executed first.
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uint64_t NumInitialBytes = FuncInfo->getInitialStackAdjust();
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uint64_t NumResidualBytes = MFI.getStackSize() - NumInitialBytes;
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uint64_t ArgumentPopSize = 0;
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if (RetOpcode == AArch64::TC_RETURNdi ||
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RetOpcode == AArch64::TC_RETURNxi) {
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MachineOperand &JumpTarget = MBBI->getOperand(0);
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MachineOperand &StackAdjust = MBBI->getOperand(1);
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MachineInstrBuilder MIB;
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if (RetOpcode == AArch64::TC_RETURNdi) {
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MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_Bimm));
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if (JumpTarget.isGlobal()) {
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MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
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JumpTarget.getTargetFlags());
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} else {
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assert(JumpTarget.isSymbol() && "unexpected tail call destination");
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MIB.addExternalSymbol(JumpTarget.getSymbolName(),
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JumpTarget.getTargetFlags());
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}
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} else {
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assert(RetOpcode == AArch64::TC_RETURNxi && JumpTarget.isReg()
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&& "Unexpected tail call");
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MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_BRx));
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MIB.addReg(JumpTarget.getReg(), RegState::Kill);
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}
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// Add the extra operands onto the new tail call instruction even though
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// they're not used directly (so that liveness is tracked properly etc).
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for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
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MIB->addOperand(MBBI->getOperand(i));
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// Delete the pseudo instruction TC_RETURN.
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MachineInstr *NewMI = prior(MBBI);
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MBB.erase(MBBI);
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MBBI = NewMI;
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// For a tail-call in a callee-pops-arguments environment, some or all of
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// the stack may actually be in use for the call's arguments, this is
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// calculated during LowerCall and consumed here...
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ArgumentPopSize = StackAdjust.getImm();
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} else {
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// ... otherwise the amount to pop is *all* of the argument space,
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// conveniently stored in the MachineFunctionInfo by
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// LowerFormalArguments. This will, of course, be zero for the C calling
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// convention.
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ArgumentPopSize = FuncInfo->getArgumentStackToRestore();
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}
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assert(NumInitialBytes % 16 == 0 && NumResidualBytes % 16 == 0
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&& "refusing to adjust stack by misaligned amt");
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// We may need to address callee-saved registers differently, so find out the
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// bound on the frame indices.
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const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
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int MinCSFI = 0;
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int MaxCSFI = -1;
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if (CSI.size()) {
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MinCSFI = CSI[0].getFrameIdx();
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MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
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}
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// The "residual" stack update comes first from this direction and guarantees
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// that SP is NumInitialBytes below its value on function entry, either by a
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// direct update or restoring it from the frame pointer.
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if (NumInitialBytes + ArgumentPopSize != 0) {
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emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16,
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NumInitialBytes + ArgumentPopSize);
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--MBBI;
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}
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// MBBI now points to the instruction just past the last callee-saved
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// restoration (either RET/B if NumInitialBytes == 0, or the "ADD sp, sp"
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// otherwise).
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// Now we need to find out where to put the bulk of the stack adjustment
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MachineBasicBlock::iterator FirstEpilogue = MBBI;
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while (MBBI != MBB.begin()) {
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--MBBI;
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unsigned FrameOp;
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for (FrameOp = 0; FrameOp < MBBI->getNumOperands(); ++FrameOp) {
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if (MBBI->getOperand(FrameOp).isFI())
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break;
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}
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// If this instruction doesn't have a frame index we've reached the end of
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// the callee-save restoration.
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if (FrameOp == MBBI->getNumOperands())
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break;
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// Likewise if it *is* a local reference, but not to a callee-saved object.
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int FrameIdx = MBBI->getOperand(FrameOp).getIndex();
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if (FrameIdx < MinCSFI || FrameIdx > MaxCSFI)
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break;
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FirstEpilogue = MBBI;
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}
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if (MF.getFrameInfo()->hasVarSizedObjects()) {
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int64_t StaticFrameBase;
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StaticFrameBase = -(NumInitialBytes + FuncInfo->getFramePointerOffset());
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emitRegUpdate(MBB, FirstEpilogue, DL, TII,
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AArch64::XSP, AArch64::X29, AArch64::NoRegister,
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StaticFrameBase);
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} else {
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emitSPUpdate(MBB, FirstEpilogue, DL,TII, AArch64::X16, NumResidualBytes);
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}
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}
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int64_t
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AArch64FrameLowering::resolveFrameIndexReference(MachineFunction &MF,
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int FrameIndex,
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unsigned &FrameReg,
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int SPAdj,
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bool IsCalleeSaveOp) const {
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AArch64MachineFunctionInfo *FuncInfo =
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MF.getInfo<AArch64MachineFunctionInfo>();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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int64_t TopOfFrameOffset = MFI->getObjectOffset(FrameIndex);
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assert(!(IsCalleeSaveOp && FuncInfo->getInitialStackAdjust() == 0)
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&& "callee-saved register in unexpected place");
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// If the frame for this function is particularly large, we adjust the stack
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// in two phases which means the callee-save related operations see a
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// different (intermediate) stack size.
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int64_t FrameRegPos;
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if (IsCalleeSaveOp) {
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FrameReg = AArch64::XSP;
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FrameRegPos = -static_cast<int64_t>(FuncInfo->getInitialStackAdjust());
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} else if (useFPForAddressing(MF)) {
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// Have to use the frame pointer since we have no idea where SP is.
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FrameReg = AArch64::X29;
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FrameRegPos = FuncInfo->getFramePointerOffset();
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} else {
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FrameReg = AArch64::XSP;
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FrameRegPos = -static_cast<int64_t>(MFI->getStackSize()) + SPAdj;
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}
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return TopOfFrameOffset - FrameRegPos;
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}
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void
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AArch64FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const {
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const AArch64RegisterInfo *RegInfo =
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static_cast<const AArch64RegisterInfo *>(MF.getTarget().getRegisterInfo());
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const AArch64InstrInfo &TII =
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*static_cast<const AArch64InstrInfo *>(MF.getTarget().getInstrInfo());
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if (hasFP(MF)) {
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MF.getRegInfo().setPhysRegUsed(AArch64::X29);
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MF.getRegInfo().setPhysRegUsed(AArch64::X30);
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}
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// If addressing of local variables is going to be more complicated than
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// shoving a base register and an offset into the instruction then we may well
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// need to scavenge registers. We should either specifically add an
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// callee-save register for this purpose or allocate an extra spill slot.
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bool BigStack =
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MFI->estimateStackSize(MF) >= TII.estimateRSStackLimit(MF)
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|| MFI->hasVarSizedObjects() // Access will be from X29: messes things up
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|| (MFI->adjustsStack() && !hasReservedCallFrame(MF));
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if (!BigStack)
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return;
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// We certainly need some slack space for the scavenger, preferably an extra
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// register.
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const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
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uint16_t ExtraReg = AArch64::NoRegister;
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for (unsigned i = 0; CSRegs[i]; ++i) {
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if (AArch64::GPR64RegClass.contains(CSRegs[i]) &&
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!MF.getRegInfo().isPhysRegUsed(CSRegs[i])) {
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ExtraReg = CSRegs[i];
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break;
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}
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}
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if (ExtraReg != 0) {
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MF.getRegInfo().setPhysRegUsed(ExtraReg);
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} else {
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assert(RS && "Expect register scavenger to be available");
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// Create a stack slot for scavenging purposes. PrologEpilogInserter
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// helpfully places it near either SP or FP for us to avoid
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// infinitely-regression during scavenging.
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const TargetRegisterClass *RC = &AArch64::GPR64RegClass;
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RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
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RC->getAlignment(),
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false));
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}
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}
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bool AArch64FrameLowering::determinePrologueDeath(MachineBasicBlock &MBB,
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unsigned Reg) const {
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// If @llvm.returnaddress is called then it will refer to X30 by some means;
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// the prologue store does not kill the register.
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if (Reg == AArch64::X30) {
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if (MBB.getParent()->getFrameInfo()->isReturnAddressTaken()
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&& MBB.getParent()->getRegInfo().isLiveIn(Reg))
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return false;
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}
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// In all other cases, physical registers are dead after they've been saved
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// but live at the beginning of the prologue block.
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MBB.addLiveIn(Reg);
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return true;
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}
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void
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AArch64FrameLowering::emitFrameMemOps(bool isPrologue, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI,
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LoadStoreMethod PossClasses[],
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unsigned NumClasses) const {
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DebugLoc DL = MBB.findDebugLoc(MBBI);
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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// A certain amount of implicit contract is present here. The actual stack
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// offsets haven't been allocated officially yet, so for strictly correct code
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// we rely on the fact that the elements of CSI are allocated in order
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// starting at SP, purely as dictated by size and alignment. In practice since
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// this function handles the only accesses to those slots it's not quite so
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// important.
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//
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// We have also ordered the Callee-saved register list in AArch64CallingConv
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// so that the above scheme puts registers in order: in particular we want
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// &X30 to be &X29+8 for an ABI-correct frame record (PCS 5.2.2)
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for (unsigned i = 0, e = CSI.size(); i < e; ++i) {
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unsigned Reg = CSI[i].getReg();
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// First we need to find out which register class the register belongs to so
|
|
// that we can use the correct load/store instrucitons.
|
|
unsigned ClassIdx;
|
|
for (ClassIdx = 0; ClassIdx < NumClasses; ++ClassIdx) {
|
|
if (PossClasses[ClassIdx].RegClass->contains(Reg))
|
|
break;
|
|
}
|
|
assert(ClassIdx != NumClasses
|
|
&& "Asked to store register in unexpected class");
|
|
const TargetRegisterClass &TheClass = *PossClasses[ClassIdx].RegClass;
|
|
|
|
// Now we need to decide whether it's possible to emit a paired instruction:
|
|
// for this we want the next register to be in the same class.
|
|
MachineInstrBuilder NewMI;
|
|
bool Pair = false;
|
|
if (i + 1 < CSI.size() && TheClass.contains(CSI[i+1].getReg())) {
|
|
Pair = true;
|
|
unsigned StLow = 0, StHigh = 0;
|
|
if (isPrologue) {
|
|
// Most of these registers will be live-in to the MBB and killed by our
|
|
// store, though there are exceptions (see determinePrologueDeath).
|
|
StLow = getKillRegState(determinePrologueDeath(MBB, CSI[i+1].getReg()));
|
|
StHigh = getKillRegState(determinePrologueDeath(MBB, CSI[i].getReg()));
|
|
} else {
|
|
StLow = RegState::Define;
|
|
StHigh = RegState::Define;
|
|
}
|
|
|
|
NewMI = BuildMI(MBB, MBBI, DL, TII.get(PossClasses[ClassIdx].PairOpcode))
|
|
.addReg(CSI[i+1].getReg(), StLow)
|
|
.addReg(CSI[i].getReg(), StHigh);
|
|
|
|
// If it's a paired op, we've consumed two registers
|
|
++i;
|
|
} else {
|
|
unsigned State;
|
|
if (isPrologue) {
|
|
State = getKillRegState(determinePrologueDeath(MBB, CSI[i].getReg()));
|
|
} else {
|
|
State = RegState::Define;
|
|
}
|
|
|
|
NewMI = BuildMI(MBB, MBBI, DL,
|
|
TII.get(PossClasses[ClassIdx].SingleOpcode))
|
|
.addReg(CSI[i].getReg(), State);
|
|
}
|
|
|
|
// Note that the FrameIdx refers to the second register in a pair: it will
|
|
// be allocated the smaller numeric address and so is the one an LDP/STP
|
|
// address must use.
|
|
int FrameIdx = CSI[i].getFrameIdx();
|
|
MachineMemOperand::MemOperandFlags Flags;
|
|
Flags = isPrologue ? MachineMemOperand::MOStore : MachineMemOperand::MOLoad;
|
|
MachineMemOperand *MMO =
|
|
MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
|
|
Flags,
|
|
Pair ? TheClass.getSize() * 2 : TheClass.getSize(),
|
|
MFI.getObjectAlignment(FrameIdx));
|
|
|
|
NewMI.addFrameIndex(FrameIdx)
|
|
.addImm(0) // address-register offset
|
|
.addMemOperand(MMO);
|
|
|
|
if (isPrologue)
|
|
NewMI.setMIFlags(MachineInstr::FrameSetup);
|
|
|
|
// For aesthetic reasons, during an epilogue we want to emit complementary
|
|
// operations to the prologue, but in the opposite order. So we still
|
|
// iterate through the CalleeSavedInfo list in order, but we put the
|
|
// instructions successively earlier in the MBB.
|
|
if (!isPrologue)
|
|
--MBBI;
|
|
}
|
|
}
|
|
|
|
bool
|
|
AArch64FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
const std::vector<CalleeSavedInfo> &CSI,
|
|
const TargetRegisterInfo *TRI) const {
|
|
if (CSI.empty())
|
|
return false;
|
|
|
|
static LoadStoreMethod PossibleClasses[] = {
|
|
{&AArch64::GPR64RegClass, AArch64::LSPair64_STR, AArch64::LS64_STR},
|
|
{&AArch64::FPR64RegClass, AArch64::LSFPPair64_STR, AArch64::LSFP64_STR},
|
|
};
|
|
unsigned NumClasses = llvm::array_lengthof(PossibleClasses);
|
|
|
|
emitFrameMemOps(/* isPrologue = */ true, MBB, MBBI, CSI, TRI,
|
|
PossibleClasses, NumClasses);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool
|
|
AArch64FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MBBI,
|
|
const std::vector<CalleeSavedInfo> &CSI,
|
|
const TargetRegisterInfo *TRI) const {
|
|
|
|
if (CSI.empty())
|
|
return false;
|
|
|
|
static LoadStoreMethod PossibleClasses[] = {
|
|
{&AArch64::GPR64RegClass, AArch64::LSPair64_LDR, AArch64::LS64_LDR},
|
|
{&AArch64::FPR64RegClass, AArch64::LSFPPair64_LDR, AArch64::LSFP64_LDR},
|
|
};
|
|
unsigned NumClasses = llvm::array_lengthof(PossibleClasses);
|
|
|
|
emitFrameMemOps(/* isPrologue = */ false, MBB, MBBI, CSI, TRI,
|
|
PossibleClasses, NumClasses);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool
|
|
AArch64FrameLowering::hasFP(const MachineFunction &MF) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
const TargetRegisterInfo *RI = MF.getTarget().getRegisterInfo();
|
|
|
|
// This is a decision of ABI compliance. The AArch64 PCS gives various options
|
|
// for conformance, and even at the most stringent level more or less permits
|
|
// elimination for leaf functions because there's no loss of functionality
|
|
// (for debugging etc)..
|
|
if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->hasCalls())
|
|
return true;
|
|
|
|
// The following are hard-limits: incorrect code will be generated if we try
|
|
// to omit the frame.
|
|
return (RI->needsStackRealignment(MF) ||
|
|
MFI->hasVarSizedObjects() ||
|
|
MFI->isFrameAddressTaken());
|
|
}
|
|
|
|
bool
|
|
AArch64FrameLowering::useFPForAddressing(const MachineFunction &MF) const {
|
|
return MF.getFrameInfo()->hasVarSizedObjects();
|
|
}
|
|
|
|
bool
|
|
AArch64FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
// Of the various reasons for having a frame pointer, it's actually only
|
|
// variable-sized objects that prevent reservation of a call frame.
|
|
return !(hasFP(MF) && MFI->hasVarSizedObjects());
|
|
}
|
|
|
|
void
|
|
AArch64FrameLowering::eliminateCallFramePseudoInstr(
|
|
MachineFunction &MF,
|
|
MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI) const {
|
|
const AArch64InstrInfo &TII =
|
|
*static_cast<const AArch64InstrInfo *>(MF.getTarget().getInstrInfo());
|
|
DebugLoc dl = MI->getDebugLoc();
|
|
int Opcode = MI->getOpcode();
|
|
bool IsDestroy = Opcode == TII.getCallFrameDestroyOpcode();
|
|
uint64_t CalleePopAmount = IsDestroy ? MI->getOperand(1).getImm() : 0;
|
|
|
|
if (!hasReservedCallFrame(MF)) {
|
|
unsigned Align = getStackAlignment();
|
|
|
|
int64_t Amount = MI->getOperand(0).getImm();
|
|
Amount = RoundUpToAlignment(Amount, Align);
|
|
if (!IsDestroy) Amount = -Amount;
|
|
|
|
// N.b. if CalleePopAmount is valid but zero (i.e. callee would pop, but it
|
|
// doesn't have to pop anything), then the first operand will be zero too so
|
|
// this adjustment is a no-op.
|
|
if (CalleePopAmount == 0) {
|
|
// FIXME: in-function stack adjustment for calls is limited to 12-bits
|
|
// because there's no guaranteed temporary register available. Mostly call
|
|
// frames will be allocated at the start of a function so this is OK, but
|
|
// it is a limitation that needs dealing with.
|
|
assert(Amount > -0xfff && Amount < 0xfff && "call frame too large");
|
|
emitSPUpdate(MBB, MI, dl, TII, AArch64::NoRegister, Amount);
|
|
}
|
|
} else if (CalleePopAmount != 0) {
|
|
// If the calling convention demands that the callee pops arguments from the
|
|
// stack, we want to add it back if we have a reserved call frame.
|
|
assert(CalleePopAmount < 0xfff && "call frame too large");
|
|
emitSPUpdate(MBB, MI, dl, TII, AArch64::NoRegister, -CalleePopAmount);
|
|
}
|
|
|
|
MBB.erase(MI);
|
|
}
|