mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
af2fa71a64
Summary: Make use of isAtLeastRelease/Acquire in the ARM/AArch64 backends These helper functions are introduced in D4844. Depends D4844 Test Plan: make check-all passes Reviewers: jfb Subscribers: aemerson, llvm-commits, mcrosier, reames Differential Revision: http://reviews.llvm.org/D4937 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215902 91177308-0d34-0410-b5e6-96231b3b80d8
364 lines
16 KiB
TableGen
364 lines
16 KiB
TableGen
//=- AArch64InstrAtomics.td - AArch64 Atomic codegen support -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// AArch64 Atomic operand code-gen constructs.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------
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// Atomic fences
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//===----------------------------------
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def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>;
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def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>;
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//===----------------------------------
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// Atomic loads
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//===----------------------------------
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// When they're actually atomic, only one addressing mode (GPR64sp) is
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// supported, but when they're relaxed and anything can be used, all the
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// standard modes would be valid and may give efficiency gains.
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// A atomic load operation that actually needs acquire semantics.
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class acquiring_load<PatFrag base>
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: PatFrag<(ops node:$ptr), (base node:$ptr), [{
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AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
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return isAtLeastAcquire(Ordering);
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}]>;
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// An atomic load operation that does not need either acquire or release
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// semantics.
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class relaxed_load<PatFrag base>
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: PatFrag<(ops node:$ptr), (base node:$ptr), [{
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AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
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return !isAtLeastAcquire(Ordering);
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}]>;
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// 8-bit loads
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def : Pat<(acquiring_load<atomic_load_8> GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
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def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
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ro_Wextend8:$offset)),
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(LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
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def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
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ro_Xextend8:$offset)),
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(LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
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def : Pat<(relaxed_load<atomic_load_8> (am_indexed8 GPR64sp:$Rn,
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uimm12s1:$offset)),
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(LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
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def : Pat<(relaxed_load<atomic_load_8>
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(am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
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(LDURBBi GPR64sp:$Rn, simm9:$offset)>;
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// 16-bit loads
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def : Pat<(acquiring_load<atomic_load_16> GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>;
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def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
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ro_Wextend16:$extend)),
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(LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
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def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
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ro_Xextend16:$extend)),
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(LDRHHroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
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def : Pat<(relaxed_load<atomic_load_16> (am_indexed16 GPR64sp:$Rn,
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uimm12s2:$offset)),
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(LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
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def : Pat<(relaxed_load<atomic_load_16>
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(am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
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(LDURHHi GPR64sp:$Rn, simm9:$offset)>;
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// 32-bit loads
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def : Pat<(acquiring_load<atomic_load_32> GPR64sp:$ptr), (LDARW GPR64sp:$ptr)>;
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def : Pat<(relaxed_load<atomic_load_32> (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
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ro_Wextend32:$extend)),
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(LDRWroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
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def : Pat<(relaxed_load<atomic_load_32> (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
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ro_Xextend32:$extend)),
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(LDRWroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>;
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def : Pat<(relaxed_load<atomic_load_32> (am_indexed32 GPR64sp:$Rn,
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uimm12s4:$offset)),
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(LDRWui GPR64sp:$Rn, uimm12s4:$offset)>;
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def : Pat<(relaxed_load<atomic_load_32>
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(am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
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(LDURWi GPR64sp:$Rn, simm9:$offset)>;
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// 64-bit loads
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def : Pat<(acquiring_load<atomic_load_64> GPR64sp:$ptr), (LDARX GPR64sp:$ptr)>;
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def : Pat<(relaxed_load<atomic_load_64> (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
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ro_Wextend64:$extend)),
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(LDRXroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
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def : Pat<(relaxed_load<atomic_load_64> (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
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ro_Xextend64:$extend)),
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(LDRXroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
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def : Pat<(relaxed_load<atomic_load_64> (am_indexed64 GPR64sp:$Rn,
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uimm12s8:$offset)),
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(LDRXui GPR64sp:$Rn, uimm12s8:$offset)>;
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def : Pat<(relaxed_load<atomic_load_64>
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(am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
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(LDURXi GPR64sp:$Rn, simm9:$offset)>;
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//===----------------------------------
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// Atomic stores
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//===----------------------------------
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// When they're actually atomic, only one addressing mode (GPR64sp) is
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// supported, but when they're relaxed and anything can be used, all the
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// standard modes would be valid and may give efficiency gains.
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// A store operation that actually needs release semantics.
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class releasing_store<PatFrag base>
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: PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
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AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
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assert(Ordering != AcquireRelease && "unexpected store ordering");
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return isAtLeastRelease(Ordering);
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}]>;
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// An atomic store operation that doesn't actually need to be atomic on AArch64.
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class relaxed_store<PatFrag base>
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: PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
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AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
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return !isAtLeastRelease(Ordering);
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}]>;
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// 8-bit stores
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def : Pat<(releasing_store<atomic_store_8> GPR64sp:$ptr, GPR32:$val),
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(STLRB GPR32:$val, GPR64sp:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_8>
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(ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
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GPR32:$val),
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(STRBBroW GPR32:$val, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend)>;
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def : Pat<(relaxed_store<atomic_store_8>
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(ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
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GPR32:$val),
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(STRBBroX GPR32:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend)>;
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def : Pat<(relaxed_store<atomic_store_8>
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(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset), GPR32:$val),
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(STRBBui GPR32:$val, GPR64sp:$Rn, uimm12s1:$offset)>;
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def : Pat<(relaxed_store<atomic_store_8>
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(am_unscaled8 GPR64sp:$Rn, simm9:$offset), GPR32:$val),
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(STURBBi GPR32:$val, GPR64sp:$Rn, simm9:$offset)>;
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// 16-bit stores
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def : Pat<(releasing_store<atomic_store_16> GPR64sp:$ptr, GPR32:$val),
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(STLRH GPR32:$val, GPR64sp:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
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ro_Wextend16:$extend),
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GPR32:$val),
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(STRHHroW GPR32:$val, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
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def : Pat<(relaxed_store<atomic_store_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
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ro_Xextend16:$extend),
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GPR32:$val),
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(STRHHroX GPR32:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend)>;
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def : Pat<(relaxed_store<atomic_store_16>
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(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset), GPR32:$val),
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(STRHHui GPR32:$val, GPR64sp:$Rn, uimm12s2:$offset)>;
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def : Pat<(relaxed_store<atomic_store_16>
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(am_unscaled16 GPR64sp:$Rn, simm9:$offset), GPR32:$val),
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(STURHHi GPR32:$val, GPR64sp:$Rn, simm9:$offset)>;
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// 32-bit stores
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def : Pat<(releasing_store<atomic_store_32> GPR64sp:$ptr, GPR32:$val),
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(STLRW GPR32:$val, GPR64sp:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_32> (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
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ro_Wextend32:$extend),
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GPR32:$val),
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(STRWroW GPR32:$val, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
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def : Pat<(relaxed_store<atomic_store_32> (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
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ro_Xextend32:$extend),
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GPR32:$val),
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(STRWroX GPR32:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)>;
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def : Pat<(relaxed_store<atomic_store_32>
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(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset), GPR32:$val),
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(STRWui GPR32:$val, GPR64sp:$Rn, uimm12s4:$offset)>;
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def : Pat<(relaxed_store<atomic_store_32>
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(am_unscaled32 GPR64sp:$Rn, simm9:$offset), GPR32:$val),
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(STURWi GPR32:$val, GPR64sp:$Rn, simm9:$offset)>;
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// 64-bit stores
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def : Pat<(releasing_store<atomic_store_64> GPR64sp:$ptr, GPR64:$val),
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(STLRX GPR64:$val, GPR64sp:$ptr)>;
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def : Pat<(relaxed_store<atomic_store_64> (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
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ro_Wextend16:$extend),
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GPR64:$val),
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(STRXroW GPR64:$val, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
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def : Pat<(relaxed_store<atomic_store_64> (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
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ro_Xextend16:$extend),
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GPR64:$val),
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(STRXroX GPR64:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
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def : Pat<(relaxed_store<atomic_store_64>
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(am_indexed64 GPR64sp:$Rn, uimm12s8:$offset), GPR64:$val),
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(STRXui GPR64:$val, GPR64sp:$Rn, uimm12s8:$offset)>;
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def : Pat<(relaxed_store<atomic_store_64>
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(am_unscaled64 GPR64sp:$Rn, simm9:$offset), GPR64:$val),
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(STURXi GPR64:$val, GPR64sp:$Rn, simm9:$offset)>;
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//===----------------------------------
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// Low-level exclusive operations
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//===----------------------------------
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// Load-exclusives.
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def ldxr_1 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
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}]>;
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def ldxr_2 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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def ldxr_4 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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def ldxr_8 : PatFrag<(ops node:$ptr), (int_aarch64_ldxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
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}]>;
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def : Pat<(ldxr_1 GPR64sp:$addr),
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(SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
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def : Pat<(ldxr_2 GPR64sp:$addr),
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(SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>;
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def : Pat<(ldxr_4 GPR64sp:$addr),
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(SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>;
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def : Pat<(ldxr_8 GPR64sp:$addr), (LDXRX GPR64sp:$addr)>;
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def : Pat<(and (ldxr_1 GPR64sp:$addr), 0xff),
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(SUBREG_TO_REG (i64 0), (LDXRB GPR64sp:$addr), sub_32)>;
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def : Pat<(and (ldxr_2 GPR64sp:$addr), 0xffff),
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(SUBREG_TO_REG (i64 0), (LDXRH GPR64sp:$addr), sub_32)>;
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def : Pat<(and (ldxr_4 GPR64sp:$addr), 0xffffffff),
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(SUBREG_TO_REG (i64 0), (LDXRW GPR64sp:$addr), sub_32)>;
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// Load-exclusives.
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def ldaxr_1 : PatFrag<(ops node:$ptr), (int_aarch64_ldaxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
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}]>;
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def ldaxr_2 : PatFrag<(ops node:$ptr), (int_aarch64_ldaxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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def ldaxr_4 : PatFrag<(ops node:$ptr), (int_aarch64_ldaxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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def ldaxr_8 : PatFrag<(ops node:$ptr), (int_aarch64_ldaxr node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
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}]>;
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def : Pat<(ldaxr_1 GPR64sp:$addr),
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(SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>;
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def : Pat<(ldaxr_2 GPR64sp:$addr),
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(SUBREG_TO_REG (i64 0), (LDAXRH GPR64sp:$addr), sub_32)>;
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def : Pat<(ldaxr_4 GPR64sp:$addr),
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(SUBREG_TO_REG (i64 0), (LDAXRW GPR64sp:$addr), sub_32)>;
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def : Pat<(ldaxr_8 GPR64sp:$addr), (LDAXRX GPR64sp:$addr)>;
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def : Pat<(and (ldaxr_1 GPR64sp:$addr), 0xff),
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(SUBREG_TO_REG (i64 0), (LDAXRB GPR64sp:$addr), sub_32)>;
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def : Pat<(and (ldaxr_2 GPR64sp:$addr), 0xffff),
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(SUBREG_TO_REG (i64 0), (LDAXRH GPR64sp:$addr), sub_32)>;
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def : Pat<(and (ldaxr_4 GPR64sp:$addr), 0xffffffff),
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(SUBREG_TO_REG (i64 0), (LDAXRW GPR64sp:$addr), sub_32)>;
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// Store-exclusives.
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def stxr_1 : PatFrag<(ops node:$val, node:$ptr),
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(int_aarch64_stxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
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}]>;
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def stxr_2 : PatFrag<(ops node:$val, node:$ptr),
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(int_aarch64_stxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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def stxr_4 : PatFrag<(ops node:$val, node:$ptr),
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(int_aarch64_stxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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def stxr_8 : PatFrag<(ops node:$val, node:$ptr),
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(int_aarch64_stxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
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}]>;
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def : Pat<(stxr_1 GPR64:$val, GPR64sp:$addr),
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(STXRB (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
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def : Pat<(stxr_2 GPR64:$val, GPR64sp:$addr),
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(STXRH (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
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def : Pat<(stxr_4 GPR64:$val, GPR64sp:$addr),
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(STXRW (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
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def : Pat<(stxr_8 GPR64:$val, GPR64sp:$addr),
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(STXRX GPR64:$val, GPR64sp:$addr)>;
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def : Pat<(stxr_1 (zext (and GPR32:$val, 0xff)), GPR64sp:$addr),
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(STXRB GPR32:$val, GPR64sp:$addr)>;
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def : Pat<(stxr_2 (zext (and GPR32:$val, 0xffff)), GPR64sp:$addr),
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(STXRH GPR32:$val, GPR64sp:$addr)>;
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def : Pat<(stxr_4 (zext GPR32:$val), GPR64sp:$addr),
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(STXRW GPR32:$val, GPR64sp:$addr)>;
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def : Pat<(stxr_1 (and GPR64:$val, 0xff), GPR64sp:$addr),
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(STXRB (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
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def : Pat<(stxr_2 (and GPR64:$val, 0xffff), GPR64sp:$addr),
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(STXRH (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
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def : Pat<(stxr_4 (and GPR64:$val, 0xffffffff), GPR64sp:$addr),
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(STXRW (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
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// Store-release-exclusives.
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def stlxr_1 : PatFrag<(ops node:$val, node:$ptr),
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(int_aarch64_stlxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
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}]>;
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def stlxr_2 : PatFrag<(ops node:$val, node:$ptr),
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(int_aarch64_stlxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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def stlxr_4 : PatFrag<(ops node:$val, node:$ptr),
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(int_aarch64_stlxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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def stlxr_8 : PatFrag<(ops node:$val, node:$ptr),
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(int_aarch64_stlxr node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
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}]>;
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def : Pat<(stlxr_1 GPR64:$val, GPR64sp:$addr),
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(STLXRB (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
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def : Pat<(stlxr_2 GPR64:$val, GPR64sp:$addr),
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(STLXRH (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
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def : Pat<(stlxr_4 GPR64:$val, GPR64sp:$addr),
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(STLXRW (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
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def : Pat<(stlxr_8 GPR64:$val, GPR64sp:$addr),
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(STLXRX GPR64:$val, GPR64sp:$addr)>;
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def : Pat<(stlxr_1 (zext (and GPR32:$val, 0xff)), GPR64sp:$addr),
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(STLXRB GPR32:$val, GPR64sp:$addr)>;
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def : Pat<(stlxr_2 (zext (and GPR32:$val, 0xffff)), GPR64sp:$addr),
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(STLXRH GPR32:$val, GPR64sp:$addr)>;
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def : Pat<(stlxr_4 (zext GPR32:$val), GPR64sp:$addr),
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(STLXRW GPR32:$val, GPR64sp:$addr)>;
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def : Pat<(stlxr_1 (and GPR64:$val, 0xff), GPR64sp:$addr),
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(STLXRB (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
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def : Pat<(stlxr_2 (and GPR64:$val, 0xffff), GPR64sp:$addr),
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(STLXRH (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
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def : Pat<(stlxr_4 (and GPR64:$val, 0xffffffff), GPR64sp:$addr),
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(STLXRW (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
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// And clear exclusive.
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def : Pat<(int_aarch64_clrex), (CLREX 0xf)>;
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