Daniel Sanders 77ae274ae7 [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6 ... Summary: There is no change to the restrictions, just the result register is stored once in the encoding rather than twice. The rt field is zero in MIPS32r6/MIPS64r6. Depends on D4119 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4120 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211019 91177308-0d34-0410-b5e6-96231b3b80d8		2014-06-16 13:18:59 +00:00
..
AArch64	Condition codes AL and NV are invalid in the aliases that use	2014-06-10 13:11:35 +00:00
ARM	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
AsmParser	Rearrange the CHECK lines in this test to make failure more obvious.	2014-06-10 20:16:47 +00:00
COFF	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Disassembler	[mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6	2014-06-16 13:18:59 +00:00
ELF	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
MachO	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Markup
Mips	[mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6	2014-06-16 13:18:59 +00:00
PowerPC	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Sparc	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
SystemZ	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
X86	[X86] AVX512: Add vmovntdqa	2014-06-10 16:39:53 +00:00