Evan Cheng 298ebf2bd8 If the false case is the current basic block, then this is a self loop. ... We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra instruction in the loop. Instead, invert the condition and emit "Loop: ... br!cond Loop; br Out. Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26231 91177308-0d34-0410-b5e6-96231b3b80d8		2006-02-16 08:27:56 +00:00
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SelectionDAG	If the false case is the current basic block, then this is a self loop.	2006-02-16 08:27:56 +00:00
AsmPrinter.cpp
BranchFolding.cpp
DwarfWriter.cpp
ELFWriter.cpp
IntrinsicLowering.cpp
LiveInterval.cpp
LiveIntervalAnalysis.cpp
LiveVariables.cpp
MachineBasicBlock.cpp
MachineCodeEmitter.cpp
MachineDebugInfo.cpp
MachineFunction.cpp
MachineInstr.cpp
Makefile
Passes.cpp
PHIElimination.cpp
PhysRegTracker.h
PrologEpilogInserter.cpp
RegAllocLinearScan.cpp
RegAllocLocal.cpp
RegAllocSimple.cpp
TwoAddressInstructionPass.cpp
UnreachableBlockElim.cpp
VirtRegMap.cpp
VirtRegMap.h