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I'm about to add support for high-word operations, so it seemed better for the low-word registers to have names like R0L rather than R0W. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191655 91177308-0d34-0410-b5e6-96231b3b80d8
140 lines
5.2 KiB
C++
140 lines
5.2 KiB
C++
//===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZRegisterInfo.h"
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#include "SystemZTargetMachine.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#define GET_REGINFO_TARGET_DESC
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#include "SystemZGenRegisterInfo.inc"
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using namespace llvm;
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SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm)
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: SystemZGenRegisterInfo(SystemZ::R14D), TM(tm) {}
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const uint16_t*
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SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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static const uint16_t CalleeSavedRegs[] = {
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SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D,
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SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D,
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SystemZ::R14D, SystemZ::R15D,
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SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
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SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
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0
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};
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return CalleeSavedRegs;
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}
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BitVector
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SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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if (TFI->hasFP(MF)) {
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// R11D is the frame pointer. Reserve all aliases.
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Reserved.set(SystemZ::R11D);
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Reserved.set(SystemZ::R11L);
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Reserved.set(SystemZ::R10Q);
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}
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// R15D is the stack pointer. Reserve all aliases.
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Reserved.set(SystemZ::R15D);
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Reserved.set(SystemZ::R15L);
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Reserved.set(SystemZ::R14Q);
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return Reserved;
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}
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void
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SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
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MachineBasicBlock &MBB = *MI->getParent();
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MachineFunction &MF = *MBB.getParent();
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const SystemZInstrInfo &TII =
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*static_cast<const SystemZInstrInfo*>(TM.getInstrInfo());
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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DebugLoc DL = MI->getDebugLoc();
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// Decompose the frame index into a base and offset.
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int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
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unsigned BasePtr = getFrameRegister(MF);
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int64_t Offset = (TFI->getFrameIndexOffset(MF, FrameIndex) +
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MI->getOperand(FIOperandNum + 1).getImm());
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// Special handling of dbg_value instructions.
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if (MI->isDebugValue()) {
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MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
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MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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return;
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}
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// See if the offset is in range, or if an equivalent instruction that
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// accepts the offset exists.
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unsigned Opcode = MI->getOpcode();
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unsigned OpcodeForOffset = TII.getOpcodeForOffset(Opcode, Offset);
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if (OpcodeForOffset)
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MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
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else {
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// Create an anchor point that is in range. Start at 0xffff so that
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// can use LLILH to load the immediate.
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int64_t OldOffset = Offset;
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int64_t Mask = 0xffff;
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do {
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Offset = OldOffset & Mask;
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OpcodeForOffset = TII.getOpcodeForOffset(Opcode, Offset);
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Mask >>= 1;
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assert(Mask && "One offset must be OK");
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} while (!OpcodeForOffset);
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unsigned ScratchReg =
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MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
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int64_t HighOffset = OldOffset - Offset;
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if (MI->getDesc().TSFlags & SystemZII::HasIndex
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&& MI->getOperand(FIOperandNum + 2).getReg() == 0) {
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// Load the offset into the scratch register and use it as an index.
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// The scratch register then dies here.
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TII.loadImmediate(MBB, MI, ScratchReg, HighOffset);
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MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
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MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
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false, false, true);
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} else {
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// Load the anchor address into a scratch register.
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unsigned LAOpcode = TII.getOpcodeForOffset(SystemZ::LA, HighOffset);
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if (LAOpcode)
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BuildMI(MBB, MI, DL, TII.get(LAOpcode),ScratchReg)
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.addReg(BasePtr).addImm(HighOffset).addReg(0);
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else {
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// Load the high offset into the scratch register and use it as
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// an index.
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TII.loadImmediate(MBB, MI, ScratchReg, HighOffset);
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BuildMI(MBB, MI, DL, TII.get(SystemZ::AGR),ScratchReg)
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.addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
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}
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// Use the scratch register as the base. It then dies here.
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MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
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false, false, true);
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}
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}
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MI->setDesc(TII.get(OpcodeForOffset));
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MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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}
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unsigned
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SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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return TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D;
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}
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