mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-21 16:31:16 +00:00
cf2ab764db
All changes were made by the following bash script:
find test/CodeGen -name "*.ll" | \
while read NAME; do
echo "$NAME"
grep -q "^; *RUN: *llc.*debug" $NAME && continue
grep -q "^; *RUN:.*llvm-objdump" $NAME && continue
grep -q "^; *RUN: *opt.*" $NAME && continue
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\([A-Za-z0-9_-]*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC[:]* *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
done
sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
mv $TEMP $NAME
done
This script catches a superset of the cases caught by the script associated with commit r186280. It initially found some false positives due to unusual constructs in a minority of tests; all such cases were disambiguated first in commit r186621.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186624 91177308-0d34-0410-b5e6-96231b3b80d8
300 lines
11 KiB
LLVM
300 lines
11 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; PR11102
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define <4 x float> @test1(<4 x float> %a) nounwind {
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%b = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 undef, i32 undef>
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ret <4 x float> %b
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; CHECK-LABEL: test1:
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; CHECK: vshufps
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; CHECK: vpshufd
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}
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; rdar://10538417
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define <3 x i64> @test2(<2 x i64> %v) nounwind readnone {
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; CHECK-LABEL: test2:
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; CHECK: vinsertf128
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%1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> <i32 0, i32 1, i32 undef>
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%2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> <i32 3, i32 4, i32 2>
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ret <3 x i64> %2
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; CHECK: ret
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}
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define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind {
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%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 undef>
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ret <4 x i64> %c
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; CHECK-LABEL: test3:
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; CHECK: vperm2f128
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; CHECK: ret
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}
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define <8 x float> @test4(float %a) nounwind {
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%b = insertelement <8 x float> zeroinitializer, float %a, i32 0
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ret <8 x float> %b
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; CHECK-LABEL: test4:
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; CHECK: vinsertf128
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}
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; rdar://10594409
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define <8 x float> @test5(float* nocapture %f) nounwind uwtable readonly ssp {
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entry:
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%0 = bitcast float* %f to <4 x float>*
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%1 = load <4 x float>* %0, align 16
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; CHECK: test5
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; CHECK: vmovaps
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; CHECK-NOT: vxorps
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; CHECK-NOT: vinsertf128
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%shuffle.i = shufflevector <4 x float> %1, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
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ret <8 x float> %shuffle.i
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}
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define <4 x double> @test6(double* nocapture %d) nounwind uwtable readonly ssp {
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entry:
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%0 = bitcast double* %d to <2 x double>*
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%1 = load <2 x double>* %0, align 16
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; CHECK: test6
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; CHECK: vmovaps
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; CHECK-NOT: vxorps
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; CHECK-NOT: vinsertf128
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%shuffle.i = shufflevector <2 x double> %1, <2 x double> <double 0.000000e+00, double undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
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ret <4 x double> %shuffle.i
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}
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define <16 x i16> @test7(<4 x i16> %a) nounwind {
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; CHECK: test7
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%b = shufflevector <4 x i16> %a, <4 x i16> undef, <16 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; CHECK: ret
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ret <16 x i16> %b
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}
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; CHECK: test8
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define void @test8() {
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entry:
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%0 = load <16 x i64> addrspace(1)* null, align 128
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%1 = shufflevector <16 x i64> <i64 undef, i64 undef, i64 0, i64 undef, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 undef, i64 0, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i64> %0, <16 x i32> <i32 17, i32 18, i32 2, i32 undef, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 undef, i32 11, i32 undef, i32 undef, i32 undef, i32 26>
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%2 = shufflevector <16 x i64> %1, <16 x i64> %0, <16 x i32> <i32 0, i32 1, i32 2, i32 30, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 undef, i32 11, i32 undef, i32 22, i32 20, i32 15>
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store <16 x i64> %2, <16 x i64> addrspace(1)* undef, align 128
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; CHECK: ret
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ret void
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}
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; Extract a value from a shufflevector..
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define i32 @test9(<4 x i32> %a) nounwind {
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; CHECK: test9
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; CHECK: vpextrd
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%b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 undef, i32 4>
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%r = extractelement <8 x i32> %b, i32 2
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; CHECK: ret
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ret i32 %r
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}
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; Extract a value which is the result of an undef mask.
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define i32 @test10(<4 x i32> %a) nounwind {
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; CHECK: @test10
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; CHECK-NOT: {{^[^#]*[a-z]}}
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; CHECK: ret
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%b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%r = extractelement <8 x i32> %b, i32 2
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ret i32 %r
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}
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define <4 x float> @test11(<4 x float> %a) nounwind {
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; CHECK: test11
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; CHECK: vpshufd $27
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%tmp1 = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x float> %tmp1
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}
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define <4 x float> @test12(<4 x float>* %a) nounwind {
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; CHECK: test12
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; CHECK: vpshufd
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%tmp0 = load <4 x float>* %a
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%tmp1 = shufflevector <4 x float> %tmp0, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x float> %tmp1
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}
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define <4 x i32> @test13(<4 x i32> %a) nounwind {
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; CHECK: test13
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; CHECK: vpshufd $27
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%tmp1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i32> %tmp1
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}
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define <4 x i32> @test14(<4 x i32>* %a) nounwind {
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; CHECK: test14
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; CHECK: vpshufd $27, (
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%tmp0 = load <4 x i32>* %a
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%tmp1 = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
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ret <4 x i32> %tmp1
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}
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; CHECK: test15
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; CHECK: vpshufd $8
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; CHECK: ret
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define <4 x i32> @test15(<2 x i32>%x) nounwind readnone {
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%x1 = shufflevector <2 x i32> %x, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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ret <4 x i32>%x1
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}
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; rdar://10974078
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define <8 x float> @test16(float* nocapture %f) nounwind uwtable readonly ssp {
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entry:
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%0 = bitcast float* %f to <4 x float>*
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%1 = load <4 x float>* %0, align 8
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; CHECK: test16
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; CHECK: vmovups
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; CHECK-NOT: vxorps
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; CHECK-NOT: vinsertf128
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%shuffle.i = shufflevector <4 x float> %1, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
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ret <8 x float> %shuffle.i
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}
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; PR12413
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; CHECK: shuf1
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; CHECK: vpshufb
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; CHECK: vpshufb
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; CHECK: vpshufb
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; CHECK: vpshufb
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define <32 x i8> @shuf1(<32 x i8> %inval1, <32 x i8> %inval2) {
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entry:
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%0 = shufflevector <32 x i8> %inval1, <32 x i8> %inval2, <32 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 32, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 62>
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ret <32 x i8> %0
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}
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; handle the case where only half of the 256-bits is splittable
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; CHECK: shuf2
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; CHECK: vpshufb
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; CHECK: vpshufb
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; CHECK: vpextrb
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; CHECK: vpextrb
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define <32 x i8> @shuf2(<32 x i8> %inval1, <32 x i8> %inval2) {
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entry:
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%0 = shufflevector <32 x i8> %inval1, <32 x i8> %inval2, <32 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 31, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 62>
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ret <32 x i8> %0
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}
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; CHECK: blend1
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; CHECK: vblendps
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; CHECK: ret
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define <4 x i32> @blend1(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
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%t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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ret <4 x i32> %t
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}
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; CHECK: blend2
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; CHECK: vblendps
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; CHECK: ret
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define <4 x i32> @blend2(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
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%t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x i32> %t
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}
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; CHECK: blend2a
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; CHECK: vblendps
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; CHECK: ret
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define <4 x float> @blend2a(<4 x float> %a, <4 x float> %b) nounwind alwaysinline {
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%t = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x float> %t
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}
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; CHECK: blend3
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; CHECK-NOT: vblendps
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; CHECK: ret
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define <4 x i32> @blend3(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
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%t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 2, i32 7>
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ret <4 x i32> %t
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}
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; CHECK: blend4
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; CHECK: vblendpd
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; CHECK: ret
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define <4 x i64> @blend4(<4 x i64> %a, <4 x i64> %b) nounwind alwaysinline {
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%t = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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ret <4 x i64> %t
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}
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; CHECK: narrow
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; CHECK: vpermilps
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; CHECK: ret
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define <16 x i16> @narrow(<16 x i16> %a) nounwind alwaysinline {
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%t = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> <i32 2, i32 3, i32 undef, i32 1, i32 6, i32 7, i32 4, i32 5, i32 10, i32 11, i32 8, i32 undef, i32 14, i32 15, i32 undef, i32 undef>
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ret <16 x i16> %t
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}
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;CHECK-LABEL: test17:
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;CHECK-NOT: vinsertf128
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;CHECK: ret
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define <8 x float> @test17(<4 x float> %y) {
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%x = shufflevector <4 x float> %y, <4 x float> undef, <8 x i32> <i32 undef, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <8 x float> %x
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}
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; CHECK: test18
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; CHECK: vmovshdup
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; CHECK: vblendps
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; CHECK: ret
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define <8 x float> @test18(<8 x float> %A, <8 x float>%B) nounwind {
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%S = shufflevector <8 x float> %A, <8 x float> %B, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15>
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ret <8 x float>%S
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}
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; CHECK: test19
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; CHECK: vmovsldup
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; CHECK: vblendps
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; CHECK: ret
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define <8 x float> @test19(<8 x float> %A, <8 x float>%B) nounwind {
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%S = shufflevector <8 x float> %A, <8 x float> %B, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14>
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ret <8 x float>%S
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}
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; rdar://12684358
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; Make sure loads happen before stores.
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; CHECK: swap8doubles
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; CHECK: vmovups {{[0-9]*}}(%rdi), %xmm{{[0-9]+}}
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; CHECK: vmovups {{[0-9]*}}(%rdi), %xmm{{[0-9]+}}
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; CHECK: vmovups {{[0-9]*}}(%rdi), %xmm{{[0-9]+}}
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; CHECK: vmovups {{[0-9]*}}(%rdi), %xmm{{[0-9]+}}
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; CHECK: vmovaps {{[0-9]*}}(%rsi), %ymm{{[0-9]+}}
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; CHECK: vmovaps {{[0-9]*}}(%rsi), %ymm{{[0-9]+}}
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; CHECK: vmovaps %xmm{{[0-9]+}}, {{[0-9]*}}(%rdi)
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; CHECK: vextractf128
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; CHECK: vmovaps %xmm{{[0-9]+}}, {{[0-9]*}}(%rdi)
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; CHECK: vextractf128
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; CHECK: vmovaps %ymm{{[0-9]+}}, {{[0-9]*}}(%rsi)
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; CHECK: vmovaps %ymm{{[0-9]+}}, {{[0-9]*}}(%rsi)
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define void @swap8doubles(double* nocapture %A, double* nocapture %C) nounwind uwtable ssp {
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entry:
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%add.ptr = getelementptr inbounds double* %A, i64 2
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%v.i = bitcast double* %A to <2 x double>*
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%0 = load <2 x double>* %v.i, align 1
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%shuffle.i.i = shufflevector <2 x double> %0, <2 x double> <double 0.000000e+00, double undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
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%v1.i = bitcast double* %add.ptr to <2 x double>*
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%1 = load <2 x double>* %v1.i, align 1
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%2 = tail call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> %shuffle.i.i, <2 x double> %1, i8 1) nounwind
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%add.ptr1 = getelementptr inbounds double* %A, i64 6
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%add.ptr2 = getelementptr inbounds double* %A, i64 4
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%v.i27 = bitcast double* %add.ptr2 to <2 x double>*
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%3 = load <2 x double>* %v.i27, align 1
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%shuffle.i.i28 = shufflevector <2 x double> %3, <2 x double> <double 0.000000e+00, double undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
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%v1.i29 = bitcast double* %add.ptr1 to <2 x double>*
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%4 = load <2 x double>* %v1.i29, align 1
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%5 = tail call <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double> %shuffle.i.i28, <2 x double> %4, i8 1) nounwind
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%6 = bitcast double* %C to <4 x double>*
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%7 = load <4 x double>* %6, align 32
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%add.ptr5 = getelementptr inbounds double* %C, i64 4
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%8 = bitcast double* %add.ptr5 to <4 x double>*
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%9 = load <4 x double>* %8, align 32
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%shuffle.i26 = shufflevector <4 x double> %7, <4 x double> undef, <2 x i32> <i32 0, i32 1>
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%10 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %7, i8 1)
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%shuffle.i = shufflevector <4 x double> %9, <4 x double> undef, <2 x i32> <i32 0, i32 1>
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%11 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %9, i8 1)
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store <2 x double> %shuffle.i26, <2 x double>* %v.i, align 16
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store <2 x double> %10, <2 x double>* %v1.i, align 16
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store <2 x double> %shuffle.i, <2 x double>* %v.i27, align 16
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store <2 x double> %11, <2 x double>* %v1.i29, align 16
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store <4 x double> %2, <4 x double>* %6, align 32
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store <4 x double> %5, <4 x double>* %8, align 32
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ret void
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}
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declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone
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declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>, i8) nounwind readnone
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