Andrew Lenharth eececbab32 add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25011 91177308-0d34-0410-b5e6-96231b3b80d8

2005-12-25 17:36:48 +00:00

..

Alpha

add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG

2005-12-25 17:36:48 +00:00

CBackend

do not allow '.' in symbol names

2005-11-10 21:39:29 +00:00

IA64

unbreak calls, a few more tests should run. Tomorrow: bugpoint!

2005-12-25 14:09:08 +00:00

PowerPC

Fix one of the things in the todo file, and get a bit closer to folding

2005-12-24 01:00:15 +00:00

Skeleton

Support multiple ValueTypes per RegisterClass, needed for upcoming vector

2005-12-01 04:51:06 +00:00

Sparc

* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.

2005-12-23 22:14:32 +00:00

SparcV8

* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.

2005-12-23 22:14:32 +00:00

SparcV9

Support multiple ValueTypes per RegisterClass, needed for upcoming vector

2005-12-01 04:51:06 +00:00

X86

Let the helper functions know about X86::FR32RegClass and X86::FR64RegClass.

2005-12-24 09:48:35 +00:00

Makefile

DONT_BUILD_RELINKED is gone and implied by BUILD_ARCHIVE now

2005-10-24 02:26:13 +00:00

MRegisterInfo.cpp

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SubtargetFeature.cpp

Preparation of supporting scheduling info. Need to find info based on selected

2005-10-25 15:15:28 +00:00

Target.td

* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.

2005-12-23 22:14:32 +00:00

TargetData.cpp

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TargetFrameInfo.cpp

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TargetInstrInfo.cpp

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TargetMachine.cpp

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TargetMachineRegistry.cpp

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TargetSchedInfo.cpp

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TargetSchedule.td

add a marker

2005-10-23 22:07:20 +00:00

TargetSelectionDAG.td

support targetexternalsym

2005-12-24 23:36:59 +00:00

TargetSubtarget.cpp

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