mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 01:30:19 +00:00
3f409f7fef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119485 91177308-0d34-0410-b5e6-96231b3b80d8
78 lines
2.9 KiB
TableGen
78 lines
2.9 KiB
TableGen
//===- PTXInstrInfo.td - PTX Instruction defs -----------------*- tblgen-*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file describes the PTX instructions in TableGen format.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction format superclass
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "PTXInstrFormats.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// PTX Specific Node Definitions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def PTXexit
|
|
: SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
|
|
def PTXret
|
|
: SDNode<"PTXISD::RET", SDTNone, [SDNPHasChain]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Class Templates
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
multiclass INT3<string opcstr, SDNode opnode> {
|
|
def rr : InstPTX<(outs RRegs32:$d),
|
|
(ins RRegs32:$a, RRegs32:$b),
|
|
!strconcat(opcstr, ".%type\t$d, $a, $b"),
|
|
[(set RRegs32:$d, (opnode RRegs32:$a, RRegs32:$b))]>;
|
|
def ri : InstPTX<(outs RRegs32:$d),
|
|
(ins RRegs32:$a, i32imm:$b),
|
|
!strconcat(opcstr, ".%type\t$d, $a, $b"),
|
|
[(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
///===- Integer Arithmetic Instructions -----------------------------------===//
|
|
|
|
defm ADD : INT3<"add", add>;
|
|
defm SUB : INT3<"sub", sub>;
|
|
|
|
///===- Data Movement and Conversion Instructions -------------------------===//
|
|
|
|
let neverHasSideEffects = 1 in {
|
|
// rely on isMoveInstr to separate MOVpp, MOVrr, etc.
|
|
def MOVpp
|
|
: InstPTX<(outs Preds:$d), (ins Preds:$a), "mov.pred\t$d, $a", []>;
|
|
def MOVrr
|
|
: InstPTX<(outs RRegs32:$d), (ins RRegs32:$a), "mov.%type\t$d, $a", []>;
|
|
}
|
|
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
|
|
def MOVpi
|
|
: InstPTX<(outs Preds:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
|
|
[(set Preds:$d, imm:$a)]>;
|
|
def MOVri
|
|
: InstPTX<(outs RRegs32:$d), (ins i32imm:$a), "mov.s32\t$d, $a",
|
|
[(set RRegs32:$d, imm:$a)]>;
|
|
}
|
|
|
|
///===- Control Flow Instructions -----------------------------------------===//
|
|
|
|
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
|
|
def EXIT : InstPTX<(outs), (ins), "exit", [(PTXexit)]>;
|
|
def RET : InstPTX<(outs), (ins), "ret", [(PTXret)]>;
|
|
}
|