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1edc3cf65d
In particular, don't repeatedly recompute the PIC base live range after rematerialization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129275 91177308-0d34-0410-b5e6-96231b3b80d8
309 lines
11 KiB
C++
309 lines
11 KiB
C++
//===--- LiveRangeEdit.cpp - Basic tools for editing a register live range --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The LiveRangeEdit class represents changes done to a virtual register when it
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// is spilled or split.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "LiveRangeEdit.h"
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#include "VirtRegMap.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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LiveInterval &LiveRangeEdit::createFrom(unsigned OldReg,
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LiveIntervals &LIS,
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VirtRegMap &VRM) {
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MachineRegisterInfo &MRI = VRM.getRegInfo();
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unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
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VRM.grow();
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VRM.setIsSplitFromReg(VReg, VRM.getOriginal(OldReg));
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LiveInterval &LI = LIS.getOrCreateInterval(VReg);
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newRegs_.push_back(&LI);
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return LI;
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}
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void LiveRangeEdit::checkRematerializable(VNInfo *VNI,
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const MachineInstr *DefMI,
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const TargetInstrInfo &tii,
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AliasAnalysis *aa) {
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assert(DefMI && "Missing instruction");
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if (tii.isTriviallyReMaterializable(DefMI, aa))
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remattable_.insert(VNI);
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scannedRemattable_ = true;
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}
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void LiveRangeEdit::scanRemattable(LiveIntervals &lis,
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const TargetInstrInfo &tii,
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AliasAnalysis *aa) {
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for (LiveInterval::vni_iterator I = parent_.vni_begin(),
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E = parent_.vni_end(); I != E; ++I) {
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VNInfo *VNI = *I;
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if (VNI->isUnused())
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continue;
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MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def);
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if (!DefMI)
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continue;
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checkRematerializable(VNI, DefMI, tii, aa);
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}
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}
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bool LiveRangeEdit::anyRematerializable(LiveIntervals &lis,
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const TargetInstrInfo &tii,
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AliasAnalysis *aa) {
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if (!scannedRemattable_)
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scanRemattable(lis, tii, aa);
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return !remattable_.empty();
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}
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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/// OrigIdx are also available with the same value at UseIdx.
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bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
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SlotIndex OrigIdx,
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SlotIndex UseIdx,
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LiveIntervals &lis) {
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OrigIdx = OrigIdx.getUseIndex();
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UseIdx = UseIdx.getUseIndex();
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for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = OrigMI->getOperand(i);
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if (!MO.isReg() || !MO.getReg() || MO.isDef())
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continue;
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// Reserved registers are OK.
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if (MO.isUndef() || !lis.hasInterval(MO.getReg()))
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continue;
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// We cannot depend on virtual registers in uselessRegs_.
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if (uselessRegs_)
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for (unsigned ui = 0, ue = uselessRegs_->size(); ui != ue; ++ui)
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if ((*uselessRegs_)[ui]->reg == MO.getReg())
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return false;
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LiveInterval &li = lis.getInterval(MO.getReg());
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const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
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if (!OVNI)
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continue;
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if (OVNI != li.getVNInfoAt(UseIdx))
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return false;
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}
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return true;
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}
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bool LiveRangeEdit::canRematerializeAt(Remat &RM,
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SlotIndex UseIdx,
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bool cheapAsAMove,
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LiveIntervals &lis) {
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assert(scannedRemattable_ && "Call anyRematerializable first");
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// Use scanRemattable info.
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if (!remattable_.count(RM.ParentVNI))
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return false;
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// No defining instruction provided.
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SlotIndex DefIdx;
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if (RM.OrigMI)
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DefIdx = lis.getInstructionIndex(RM.OrigMI);
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else {
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DefIdx = RM.ParentVNI->def;
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RM.OrigMI = lis.getInstructionFromIndex(DefIdx);
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assert(RM.OrigMI && "No defining instruction for remattable value");
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}
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// If only cheap remats were requested, bail out early.
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if (cheapAsAMove && !RM.OrigMI->getDesc().isAsCheapAsAMove())
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return false;
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// Verify that all used registers are available with the same values.
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if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx, lis))
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return false;
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return true;
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}
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SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg,
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const Remat &RM,
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LiveIntervals &lis,
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const TargetInstrInfo &tii,
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const TargetRegisterInfo &tri) {
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assert(RM.OrigMI && "Invalid remat");
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tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
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rematted_.insert(RM.ParentVNI);
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return lis.InsertMachineInstrInMaps(--MI).getDefIndex();
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}
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void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) {
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if (delegate_ && delegate_->LRE_CanEraseVirtReg(Reg))
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LIS.removeInterval(Reg);
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}
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bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
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SmallVectorImpl<MachineInstr*> &Dead,
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MachineRegisterInfo &MRI,
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LiveIntervals &LIS,
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const TargetInstrInfo &TII) {
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MachineInstr *DefMI = 0, *UseMI = 0;
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// Check that there is a single def and a single use.
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for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(LI->reg),
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E = MRI.reg_nodbg_end(); I != E; ++I) {
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MachineOperand &MO = I.getOperand();
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MachineInstr *MI = MO.getParent();
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if (MO.isDef()) {
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if (DefMI && DefMI != MI)
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return false;
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if (!MI->getDesc().canFoldAsLoad())
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return false;
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DefMI = MI;
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} else if (!MO.isUndef()) {
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if (UseMI && UseMI != MI)
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return false;
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// FIXME: Targets don't know how to fold subreg uses.
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if (MO.getSubReg())
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return false;
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UseMI = MI;
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}
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}
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if (!DefMI || !UseMI)
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return false;
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DEBUG(dbgs() << "Try to fold single def: " << *DefMI
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<< " into single use: " << *UseMI);
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SmallVector<unsigned, 8> Ops;
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if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
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return false;
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MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI);
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if (!FoldMI)
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return false;
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DEBUG(dbgs() << " folded: " << *FoldMI);
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LIS.ReplaceMachineInstrInMaps(UseMI, FoldMI);
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UseMI->eraseFromParent();
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DefMI->addRegisterDead(LI->reg, 0);
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Dead.push_back(DefMI);
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return true;
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}
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void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
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LiveIntervals &LIS, VirtRegMap &VRM,
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const TargetInstrInfo &TII) {
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SetVector<LiveInterval*,
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SmallVector<LiveInterval*, 8>,
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SmallPtrSet<LiveInterval*, 8> > ToShrink;
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MachineRegisterInfo &MRI = VRM.getRegInfo();
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for (;;) {
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// Erase all dead defs.
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while (!Dead.empty()) {
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MachineInstr *MI = Dead.pop_back_val();
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assert(MI->allDefsAreDead() && "Def isn't really dead");
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SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
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// Never delete inline asm.
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if (MI->isInlineAsm()) {
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DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
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continue;
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}
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// Use the same criteria as DeadMachineInstructionElim.
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bool SawStore = false;
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if (!MI->isSafeToMove(&TII, 0, SawStore)) {
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DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
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continue;
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}
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DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
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// Check for live intervals that may shrink
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for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
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MOE = MI->operands_end(); MOI != MOE; ++MOI) {
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if (!MOI->isReg())
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continue;
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unsigned Reg = MOI->getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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LiveInterval &LI = LIS.getInterval(Reg);
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// Shrink read registers, unless it is likely to be expensive and
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// unlikely to change anything. We typically don't want to shrink the
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// PIC base register that has lots of uses everywhere.
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// Always shrink COPY uses that probably come from live range splitting.
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if (MI->readsVirtualRegister(Reg) &&
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(MI->isCopy() || MOI->isDef() || MRI.hasOneNonDBGUse(Reg) ||
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LI.killedAt(Idx)))
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ToShrink.insert(&LI);
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// Remove defined value.
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if (MOI->isDef()) {
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if (VNInfo *VNI = LI.getVNInfoAt(Idx)) {
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if (delegate_)
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delegate_->LRE_WillShrinkVirtReg(LI.reg);
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LI.removeValNo(VNI);
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if (LI.empty()) {
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ToShrink.remove(&LI);
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eraseVirtReg(Reg, LIS);
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}
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}
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}
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}
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if (delegate_)
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delegate_->LRE_WillEraseInstruction(MI);
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LIS.RemoveMachineInstrFromMaps(MI);
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MI->eraseFromParent();
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}
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if (ToShrink.empty())
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break;
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// Shrink just one live interval. Then delete new dead defs.
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LiveInterval *LI = ToShrink.back();
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ToShrink.pop_back();
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if (foldAsLoad(LI, Dead, MRI, LIS, TII))
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continue;
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if (delegate_)
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delegate_->LRE_WillShrinkVirtReg(LI->reg);
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if (!LIS.shrinkToUses(LI, &Dead))
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continue;
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// LI may have been separated, create new intervals.
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LI->RenumberValues(LIS);
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ConnectedVNInfoEqClasses ConEQ(LIS);
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unsigned NumComp = ConEQ.Classify(LI);
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if (NumComp <= 1)
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continue;
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DEBUG(dbgs() << NumComp << " components: " << *LI << '\n');
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SmallVector<LiveInterval*, 8> Dups(1, LI);
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for (unsigned i = 1; i != NumComp; ++i) {
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Dups.push_back(&createFrom(LI->reg, LIS, VRM));
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if (delegate_)
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delegate_->LRE_DidCloneVirtReg(Dups.back()->reg, LI->reg);
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}
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ConEQ.Distribute(&Dups[0], MRI);
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}
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}
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void LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
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LiveIntervals &LIS,
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const MachineLoopInfo &Loops) {
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VirtRegAuxInfo VRAI(MF, LIS, Loops);
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for (iterator I = begin(), E = end(); I != E; ++I) {
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LiveInterval &LI = **I;
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VRAI.CalculateRegClass(LI.reg);
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VRAI.CalculateWeightAndHint(LI);
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}
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}
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