mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-21 00:32:23 +00:00
bbe51362d5
Added fp register clobbering during calls. Added AsmPrinter support for "fmask", a bitmask that indicates where on the stack the fp callee saved registers are. Fixed the stack frame layout for Mips, now the callee saved regs are in the right stack location (a little documentation about how this stack frame must look like is present in MipsRegisterInfo.cpp). This was done using the method MipsRegisterInfo::adjustMipsStackFrame To be more clear, these are examples of what is solves : 1) FP and RA are also callee saved, and despite they aren't in CSI they must be saved before the fp callee saved registers. 2) The ABI requires that local varibles are allocated before the callee saved register area, the opposite behavior from the default allocation. 3) CPU and FPU saved register area must be aligned independent of each other. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54403 91177308-0d34-0410-b5e6-96231b3b80d8
661 lines
23 KiB
C++
661 lines
23 KiB
C++
//===- MipsInstrInfo.td - Mips Register defs --------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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include "MipsInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Mips profiles and nodes
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//===----------------------------------------------------------------------===//
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def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
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def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>,
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SDTCisSameAs<2, 3>, SDTCisInt<1>]>;
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def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
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def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
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// Call
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def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
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SDNPOutFlag]>;
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// Hi and Lo nodes are used to handle global addresses. Used on
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// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
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// static model. (nothing to do with Mips Registers Hi and Lo)
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def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
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def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
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def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
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// Return
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def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
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SDNPOptInFlag]>;
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// These are target-independent nodes, but have target-specific formats.
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
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[SDNPHasChain, SDNPOutFlag]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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// Select Condition Code
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def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
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//===----------------------------------------------------------------------===//
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// Mips Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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// Instruction operand types
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def brtarget : Operand<OtherVT>;
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def calltarget : Operand<i32>;
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def uimm16 : Operand<i32>;
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def simm16 : Operand<i32>;
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def shamt : Operand<i32>;
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// Address operand
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def mem : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops simm16, CPURegs);
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}
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// Transformation Function - get the lower 16 bits.
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def LO16 : SDNodeXForm<imm, [{
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return getI32Imm((unsigned)N->getValue() & 0xFFFF);
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}]>;
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// Transformation Function - get the higher 16 bits.
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def HI16 : SDNodeXForm<imm, [{
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return getI32Imm((unsigned)N->getValue() >> 16);
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}]>;
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// Node immediate fits as 16-bit sign extended on target immediate.
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// e.g. addi, andi
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def immSExt16 : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i32)
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return (int32_t)N->getValue() == (short)N->getValue();
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else
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return (int64_t)N->getValue() == (short)N->getValue();
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}]>;
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// Node immediate fits as 16-bit zero extended on target immediate.
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// The LO16 param means that only the lower 16 bits of the node
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// immediate are caught.
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// e.g. addiu, sltiu
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def immZExt16 : PatLeaf<(imm), [{
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if (N->getValueType(0) == MVT::i32)
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return (uint32_t)N->getValue() == (unsigned short)N->getValue();
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else
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return (uint64_t)N->getValue() == (unsigned short)N->getValue();
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}], LO16>;
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// shamt field must fit in 5 bits.
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def immZExt5 : PatLeaf<(imm), [{
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return N->getValue() == ((N->getValue()) & 0x1f) ;
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}]>;
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// Mips Address Mode! SDNode frameindex could possibily be a match
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// since load and store instructions from stack used it.
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def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], []>;
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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// Arithmetic 3 register operands
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let isCommutable = 1 in
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class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
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InstrItinClass itin>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
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let isCommutable = 1 in
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class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[], IIAlu>;
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// Arithmetic 2 register operands
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class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type> :
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
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// Arithmetic Multiply ADD/SUB
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let rd=0 in
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class MArithR<bits<6> func, string instr_asm> :
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FR< 0x1c,
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func,
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(outs CPURegs:$rs),
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(ins CPURegs:$rt),
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!strconcat(instr_asm, "\t$rs, $rt"),
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[], IIImul>;
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// Logical
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class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
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class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, uimm16:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
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class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
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// Shifts
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let rt = 0 in
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class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, shamt:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
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class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
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// Load Upper Imediate
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class LoadUpper<bits<6> op, string instr_asm>:
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FI< op,
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(outs CPURegs:$dst),
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(ins uimm16:$imm),
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!strconcat(instr_asm, "\t$dst, $imm"),
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[], IIAlu>;
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// Memory Load/Store
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let isSimpleLoad = 1, hasDelaySlot = 1 in
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class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
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FI< op,
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(outs CPURegs:$dst),
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(ins mem:$addr),
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!strconcat(instr_asm, "\t$dst, $addr"),
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[(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
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class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
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FI< op,
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(outs),
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(ins CPURegs:$dst, mem:$addr),
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!strconcat(instr_asm, "\t$dst, $addr"),
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[(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
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// Conditional Branch
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let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
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class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
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FI< op,
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(outs),
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(ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
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!strconcat(instr_asm, "\t$a, $b, $offset"),
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[(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
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IIBranch>;
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class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
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FI< op,
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(outs),
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(ins CPURegs:$src, brtarget:$offset),
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!strconcat(instr_asm, "\t$src, $offset"),
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[(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
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IIBranch>;
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}
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// SetCC
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class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
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PatFrag cond_op>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
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IIAlu>;
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class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
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Operand Od, PatLeaf imm_type>:
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
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IIAlu>;
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// Unconditional branch
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let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
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class JumpFJ<bits<6> op, string instr_asm>:
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FJ< op,
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(outs),
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(ins brtarget:$target),
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!strconcat(instr_asm, "\t$target"),
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[(br bb:$target)], IIBranch>;
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let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
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class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs),
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(ins CPURegs:$target),
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!strconcat(instr_asm, "\t$target"),
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[(brind CPURegs:$target)], IIBranch>;
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// Jump and Link (Call)
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let isCall=1, hasDelaySlot=1,
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// All calls clobber the non-callee saved registers...
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Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
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K0, K1, F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13,
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F14, F15, F16, F17, F18, F19], Uses = [GP] in {
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class JumpLink<bits<6> op, string instr_asm>:
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FJ< op,
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(outs),
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(ins calltarget:$target),
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!strconcat(instr_asm, "\t$target"),
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[(MipsJmpLink imm:$target)], IIBranch>;
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let rd=31 in
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class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs),
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(ins CPURegs:$rs),
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!strconcat(instr_asm, "\t$rs"),
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[(MipsJmpLink CPURegs:$rs)], IIBranch>;
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class BranchLink<string instr_asm>:
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FI< 0x1,
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(outs),
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(ins CPURegs:$rs, brtarget:$target),
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!strconcat(instr_asm, "\t$rs, $target"),
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[], IIBranch>;
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}
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// Mul, Div
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class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
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FR< 0x00,
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func,
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(outs),
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(ins CPURegs:$a, CPURegs:$b),
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!strconcat(instr_asm, "\t$a, $b"),
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[], itin>;
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// Move from Hi/Lo
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class MoveFromLOHI<bits<6> func, string instr_asm>:
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins),
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!strconcat(instr_asm, "\t$dst"),
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[], IIHiLo>;
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class MoveToLOHI<bits<6> func, string instr_asm>:
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FR< 0x00,
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func,
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(outs),
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(ins CPURegs:$src),
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!strconcat(instr_asm, "\t$src"),
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[], IIHiLo>;
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// Count Leading Ones/Zeros in Word
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class CountLeading<bits<6> func, string instr_asm>:
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FR< 0x1c,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"),
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[], IIAlu>;
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class EffectiveAddress<string instr_asm> :
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FI<0x09,
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(outs CPURegs:$dst),
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(ins mem:$addr),
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instr_asm,
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[(set CPURegs:$dst, addr:$addr)], IIAlu>;
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class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
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FR< 0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"),
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[(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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// As stack alignment is always done with addiu, we need a 16-bit immediate
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let Defs = [SP], Uses = [SP] in {
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def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start imm:$amt)]>;
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def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
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"!ADJCALLSTACKUP $amt1",
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[(callseq_end imm:$amt1, imm:$amt2)]>;
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}
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// Some assembly macros need to avoid pseudoinstructions and assembler
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// automatic reodering, we should reorder ourselves.
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def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
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def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
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def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
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def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
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// When handling PIC code the assembler needs .cpload and .cprestore
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// directives. If the real instructions corresponding these directives
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// are used, we have the same behavior, but get also a bunch of warnings
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// from the assembler.
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def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
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def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
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// The supported Mips ISAs dont have any instruction close to the SELECT_CC
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// operation. The solution is to create a Mips pseudo SELECT_CC instruction
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// (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally
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// replace it for real supported nodes into EmitInstrWithCustomInserter
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let usesCustomDAGSchedInserter = 1 in {
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class PseudoSelCC<RegisterClass RC, string asmstr>:
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MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr,
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[(set RC:$dst, (MipsSelectCC CPURegs:$CmpRes, RC:$T, RC:$F))]>;
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}
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def Select_CC : PseudoSelCC<CPURegs, "# MipsSelect_CC_i32">;
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//===----------------------------------------------------------------------===//
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// Instruction definition
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MipsI Instructions
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//===----------------------------------------------------------------------===//
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/// Arithmetic Instructions (ALU Immediate)
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def ADDiu : ArithI<0x09, "addiu", add, uimm16, immZExt16>;
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def ADDi : ArithI<0x08, "addi", add, simm16, immSExt16>;
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def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
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def SLTiu : SetCC_I<0x0b, "sltiu", setult, uimm16, immZExt16>;
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def ANDi : LogicI<0x0c, "andi", and>;
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def ORi : LogicI<0x0d, "ori", or>;
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def XORi : LogicI<0x0e, "xori", xor>;
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def LUi : LoadUpper<0x0f, "lui">;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
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def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
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def ADD : ArithOverflowR<0x00, 0x20, "add">;
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def SUB : ArithOverflowR<0x00, 0x22, "sub">;
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def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
|
|
def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
|
|
def AND : LogicR<0x24, "and", and>;
|
|
def OR : LogicR<0x25, "or", or>;
|
|
def XOR : LogicR<0x26, "xor", xor>;
|
|
def NOR : LogicNOR<0x00, 0x27, "nor">;
|
|
|
|
/// Shift Instructions
|
|
def SLL : LogicR_shift_imm<0x00, "sll", shl>;
|
|
def SRL : LogicR_shift_imm<0x02, "srl", srl>;
|
|
def SRA : LogicR_shift_imm<0x03, "sra", sra>;
|
|
def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
|
|
def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
|
|
def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
|
|
|
|
/// Load and Store Instructions
|
|
def LB : LoadM<0x20, "lb", sextloadi8>;
|
|
def LBu : LoadM<0x24, "lbu", zextloadi8>;
|
|
def LH : LoadM<0x21, "lh", sextloadi16>;
|
|
def LHu : LoadM<0x25, "lhu", zextloadi16>;
|
|
def LW : LoadM<0x23, "lw", load>;
|
|
def SB : StoreM<0x28, "sb", truncstorei8>;
|
|
def SH : StoreM<0x29, "sh", truncstorei16>;
|
|
def SW : StoreM<0x2b, "sw", store>;
|
|
|
|
/// Jump and Branch Instructions
|
|
def J : JumpFJ<0x02, "j">;
|
|
def JR : JumpFR<0x00, 0x08, "jr">;
|
|
def JAL : JumpLink<0x03, "jal">;
|
|
def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
|
|
def BEQ : CBranch<0x04, "beq", seteq>;
|
|
def BNE : CBranch<0x05, "bne", setne>;
|
|
|
|
let rt=1 in
|
|
def BGEZ : CBranchZero<0x01, "bgez", setge>;
|
|
|
|
let rt=0 in {
|
|
def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
|
|
def BLEZ : CBranchZero<0x07, "blez", setle>;
|
|
def BLTZ : CBranchZero<0x01, "bltz", setlt>;
|
|
}
|
|
|
|
def BGEZAL : BranchLink<"bgezal">;
|
|
def BLTZAL : BranchLink<"bltzal">;
|
|
|
|
let isReturn=1, isTerminator=1, hasDelaySlot=1,
|
|
isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
|
|
def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
|
|
"jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
|
|
|
|
/// Multiply and Divide Instructions.
|
|
let Defs = [HI, LO] in {
|
|
def MULT : MulDiv<0x18, "mult", IIImul>;
|
|
def MULTu : MulDiv<0x19, "multu", IIImul>;
|
|
def DIV : MulDiv<0x1a, "div", IIIdiv>;
|
|
def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
|
|
}
|
|
|
|
let Defs = [HI] in
|
|
def MTHI : MoveToLOHI<0x11, "mthi">;
|
|
let Defs = [LO] in
|
|
def MTLO : MoveToLOHI<0x13, "mtlo">;
|
|
|
|
let Uses = [HI] in
|
|
def MFHI : MoveFromLOHI<0x10, "mfhi">;
|
|
let Uses = [LO] in
|
|
def MFLO : MoveFromLOHI<0x12, "mflo">;
|
|
|
|
/// Sign Ext In Register Instructions.
|
|
let Predicates = [HasSEInReg] in {
|
|
let shamt = 0x10, rs = 0 in
|
|
def SEB : SignExtInReg<0x21, "seb", i8>;
|
|
|
|
let shamt = 0x18, rs = 0 in
|
|
def SEH : SignExtInReg<0x20, "seh", i16>;
|
|
}
|
|
|
|
/// No operation
|
|
let addr=0 in
|
|
def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
|
|
|
|
// FrameIndexes are legalized when they are operands from load/store
|
|
// instructions. The same not happens for stack address copies, so an
|
|
// add op with mem ComplexPattern is used and the stack address copy
|
|
// can be matched. It's similar to Sparc LEA_ADDRi
|
|
def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
|
|
|
|
// Count Leading
|
|
// CLO/CLZ are part of the newer MIPS32(tm) instruction
|
|
// set and not older Mips I keep this for future use
|
|
// though.
|
|
//def CLO : CountLeading<0x21, "clo">;
|
|
//def CLZ : CountLeading<0x20, "clz">;
|
|
|
|
// MADD*/MSUB* are not part of MipsI either.
|
|
//def MADD : MArithR<0x00, "madd">;
|
|
//def MADDU : MArithR<0x01, "maddu">;
|
|
//def MSUB : MArithR<0x04, "msub">;
|
|
//def MSUBU : MArithR<0x05, "msubu">;
|
|
|
|
// MUL is a assembly macro in the current used ISAs. In recent ISA's
|
|
// it is a real instruction.
|
|
//def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Arbitrary patterns that map to one or more instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Small immediates
|
|
def : Pat<(i32 immSExt16:$in),
|
|
(ADDiu ZERO, imm:$in)>;
|
|
def : Pat<(i32 immZExt16:$in),
|
|
(ORi ZERO, imm:$in)>;
|
|
|
|
// Arbitrary immediates
|
|
def : Pat<(i32 imm:$imm),
|
|
(ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
|
|
|
|
// Carry patterns
|
|
def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
|
|
(SUBu CPURegs:$lhs, CPURegs:$rhs)>;
|
|
def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
|
|
(ADDu CPURegs:$lhs, CPURegs:$rhs)>;
|
|
def : Pat<(addc CPURegs:$src, imm:$imm),
|
|
(ADDiu CPURegs:$src, imm:$imm)>;
|
|
|
|
// Call
|
|
def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
|
|
(JAL tglobaladdr:$dst)>;
|
|
def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
|
|
(JAL texternalsym:$dst)>;
|
|
def : Pat<(MipsJmpLink CPURegs:$dst),
|
|
(JALR CPURegs:$dst)>;
|
|
|
|
// hi/lo relocs
|
|
def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
|
|
def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
|
|
(ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
|
|
|
|
def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
|
|
def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
|
|
(ADDiu CPURegs:$hi, tjumptable:$lo)>;
|
|
|
|
def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
|
|
def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
|
|
(ADDiu CPURegs:$hi, tconstpool:$lo)>;
|
|
|
|
// gp_rel relocs
|
|
def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
|
|
(ADDiu CPURegs:$gp, tglobaladdr:$in)>;
|
|
def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
|
|
(ADDiu CPURegs:$gp, tconstpool:$in)>;
|
|
|
|
// Mips does not have "not", so we expand our way
|
|
def : Pat<(not CPURegs:$in),
|
|
(NOR CPURegs:$in, ZERO)>;
|
|
|
|
// extended load and stores
|
|
def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
|
|
def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
|
|
def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
|
|
|
|
// peepholes
|
|
def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
|
|
|
|
// brcond patterns
|
|
// direct match equal/notequal zero branches
|
|
def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
|
|
(BNE CPURegs:$lhs, ZERO, bb:$dst)>;
|
|
def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
|
|
(BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
|
|
|
|
def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
|
(BGEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
|
def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
|
(BGEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
|
|
|
def : Pat<(brcond (setgt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
|
(BGTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
|
def : Pat<(brcond (setugt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
|
(BGTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
|
|
|
def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
|
(BLEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
|
def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
|
(BLEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
|
|
|
def : Pat<(brcond (setlt CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
|
|
(BNE (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
|
|
def : Pat<(brcond (setult CPURegs:$lhs, immZExt16:$rhs), bb:$dst),
|
|
(BNE (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>;
|
|
def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
|
(BNE (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
|
|
def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
|
(BNE (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
|
|
|
|
def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
|
(BLTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
|
def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
|
|
(BLTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
|
|
|
|
// generic brcond pattern
|
|
def : Pat<(brcond CPURegs:$cond, bb:$dst),
|
|
(BNE CPURegs:$cond, ZERO, bb:$dst)>;
|
|
|
|
// setcc patterns, only matched when there
|
|
// is no brcond following a setcc operation
|
|
def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
|
|
(XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
|
|
def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
|
|
(XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
|
|
|
|
def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
|
|
(SLT CPURegs:$rhs, CPURegs:$lhs)>;
|
|
def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
|
|
(SLTu CPURegs:$rhs, CPURegs:$lhs)>;
|
|
|
|
def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
|
|
(XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
|
|
def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
|
|
(XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
|
|
|
|
def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
|
|
(OR (SLT CPURegs:$lhs, CPURegs:$rhs),
|
|
(SLT CPURegs:$rhs, CPURegs:$lhs))>;
|
|
|
|
def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
|
|
(XORi (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
|
|
(SLT CPURegs:$rhs, CPURegs:$lhs)), 1)>;
|
|
|
|
def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
|
|
(XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
|
|
def : Pat<(setuge CPURegs:$lhs, immZExt16:$rhs),
|
|
(XORi (SLTiu CPURegs:$lhs, immZExt16:$rhs), 1)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Floating Point Support
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "MipsInstrFPU.td"
|
|
|