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https://github.com/c64scene-ar/llvm-6502.git
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5a9cd4d44e
a cache of assumptions for a single function, and an immutable pass that manages those caches. The motivation for this change is two fold. Immutable analyses are really hacks around the current pass manager design and don't exist in the new design. This is usually OK, but it requires that the core logic of an immutable pass be reasonably partitioned off from the pass logic. This change does precisely that. As a consequence it also paves the way for the *many* utility functions that deal in the assumptions to live in both pass manager worlds by creating an separate non-pass object with its own independent API that they all rely on. Now, the only bits of the system that deal with the actual pass mechanics are those that actually need to deal with the pass mechanics. Once this separation is made, several simplifications become pretty obvious in the assumption cache itself. Rather than using a set and callback value handles, it can just be a vector of weak value handles. The callers can easily skip the handles that are null, and eventually we can wrap all of this up behind a filter iterator. For now, this adds boiler plate to the various passes, but this kind of boiler plate will end up making it possible to port these passes to the new pass manager, and so it will end up factored away pretty reasonably. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225131 91177308-0d34-0410-b5e6-96231b3b80d8
97 lines
3.1 KiB
C++
97 lines
3.1 KiB
C++
//===- Mem2Reg.cpp - The -mem2reg pass, a wrapper around the Utils lib ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass is a simple pass wrapper around the PromoteMemToReg function call
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// exposed by the Utils library.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AssumptionCache.h"
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#include "llvm/IR/Dominators.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/Transforms/Utils/PromoteMemToReg.h"
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#include "llvm/Transforms/Utils/UnifyFunctionExitNodes.h"
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using namespace llvm;
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#define DEBUG_TYPE "mem2reg"
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STATISTIC(NumPromoted, "Number of alloca's promoted");
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namespace {
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struct PromotePass : public FunctionPass {
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static char ID; // Pass identification, replacement for typeid
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PromotePass() : FunctionPass(ID) {
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initializePromotePassPass(*PassRegistry::getPassRegistry());
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}
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// runOnFunction - To run this pass, first we calculate the alloca
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// instructions that are safe for promotion, then we promote each one.
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//
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bool runOnFunction(Function &F) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<AssumptionCacheTracker>();
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AU.addRequired<DominatorTreeWrapperPass>();
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AU.setPreservesCFG();
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// This is a cluster of orthogonal Transforms
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AU.addPreserved<UnifyFunctionExitNodes>();
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AU.addPreservedID(LowerSwitchID);
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AU.addPreservedID(LowerInvokePassID);
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}
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};
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} // end of anonymous namespace
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char PromotePass::ID = 0;
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INITIALIZE_PASS_BEGIN(PromotePass, "mem2reg", "Promote Memory to Register",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(AssumptionCacheTracker)
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INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
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INITIALIZE_PASS_END(PromotePass, "mem2reg", "Promote Memory to Register",
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false, false)
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bool PromotePass::runOnFunction(Function &F) {
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std::vector<AllocaInst*> Allocas;
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BasicBlock &BB = F.getEntryBlock(); // Get the entry node for the function
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bool Changed = false;
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DominatorTree &DT = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
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AssumptionCache &AC =
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getAnalysis<AssumptionCacheTracker>().getAssumptionCache(F);
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while (1) {
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Allocas.clear();
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// Find allocas that are safe to promote, by looking at all instructions in
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// the entry node
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for (BasicBlock::iterator I = BB.begin(), E = --BB.end(); I != E; ++I)
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if (AllocaInst *AI = dyn_cast<AllocaInst>(I)) // Is it an alloca?
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if (isAllocaPromotable(AI))
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Allocas.push_back(AI);
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if (Allocas.empty()) break;
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PromoteMemToReg(Allocas, DT, nullptr, &AC);
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NumPromoted += Allocas.size();
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Changed = true;
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}
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return Changed;
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}
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// createPromoteMemoryToRegister - Provide an entry point to create this pass.
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//
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FunctionPass *llvm::createPromoteMemoryToRegisterPass() {
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return new PromotePass();
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}
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