mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0187e7a9ba
Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
144 lines
5.6 KiB
C++
144 lines
5.6 KiB
C++
//===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPSINSTRUCTIONINFO_H
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#define MIPSINSTRUCTIONINFO_H
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#include "Mips.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "MipsGenInstrInfo.inc"
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namespace llvm {
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class MipsInstrInfo : public MipsGenInstrInfo {
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protected:
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MipsTargetMachine &TM;
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unsigned UncondBrOpc;
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public:
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enum BranchType {
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BT_None, // Couldn't analyze branch.
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BT_NoBranch, // No branches found.
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BT_Uncond, // One unconditional branch.
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BT_Cond, // One conditional branch.
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BT_CondUncond, // A conditional branch followed by an unconditional branch.
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BT_Indirect // One indirct branch.
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};
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explicit MipsInstrInfo(MipsTargetMachine &TM, unsigned UncondBrOpc);
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static const MipsInstrInfo *create(MipsTargetMachine &TM);
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/// Branch Analysis
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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BranchType AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify,
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SmallVectorImpl<MachineInstr*> &BranchInstrs) const;
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/// Insert nop instruction when hazard condition is found
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virtual void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const;
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
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virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
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/// Return the number of bytes of code the specified instruction may be.
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unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
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}
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
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}
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virtual void storeRegToStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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int64_t Offset) const = 0;
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virtual void loadRegFromStack(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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int64_t Offset) const = 0;
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/// Create an instruction which has the same operands and memory operands
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/// as MI but has a new opcode.
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MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
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MachineBasicBlock::iterator I) const;
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protected:
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bool isZeroImm(const MachineOperand &op) const;
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MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
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unsigned Flag) const;
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private:
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virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
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void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
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MachineBasicBlock *&BB,
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SmallVectorImpl<MachineOperand> &Cond) const;
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void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
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const SmallVectorImpl<MachineOperand>& Cond) const;
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};
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/// Create MipsInstrInfo objects.
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const MipsInstrInfo *createMips16InstrInfo(MipsTargetMachine &TM);
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const MipsInstrInfo *createMipsSEInstrInfo(MipsTargetMachine &TM);
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}
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#endif
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