Ahmed Bougacha ad41590c48 [X86][MC] Intel syntax: accept implicit memory operand sizes larger than 80. ... The X86AsmParser intel handling was refactored in r216481, making it try each different memory operand size to see which one matches. Operand sizes larger than 80 ("[xyz]mmword ptr") were forgotten, which led to an "invalid operand" error for code such as: movdqa [rax], xmm0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223187 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-03 02:03:26 +00:00
..
AArch64	Update AArch64 ELF relocations to ABI 1.0	2014-11-26 10:49:18 +00:00
ARM	Introduce CPUStringIsValid() into MCSubtargetInfo and use it for ARM .cpu parsing.	2014-12-02 20:03:22 +00:00
AsmParser
COFF
Disassembler	Add support for ARM modified-immediate assembly syntax.	2014-12-02 10:53:20 +00:00
ELF	Commit back the correct bits of r222760 (was r222538).	2014-11-27 17:13:56 +00:00
Hexagon	[Hexagon] Adding cmp* immediate form instructions.	2014-11-26 19:43:12 +00:00
MachO
Markup
Mips	The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.	2014-12-01 11:12:04 +00:00
PowerPC	[PowerPC] Add asm support for cache-inhibited ld/st instructions	2014-11-30 10:15:56 +00:00
R600	R600/SI: Start implementing an assembler	2014-11-14 14:08:00 +00:00
Sparc
SystemZ
X86	[X86][MC] Intel syntax: accept implicit memory operand sizes larger than 80.	2014-12-03 02:03:26 +00:00