Evan Cheng 78fe9ababe Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during ... isel lowering to fold the zero-extend's and take advantage of no-stall back to back vmul + vmla: vmull q0, d4, d6 vmlal q0, d5, d6 is faster than vaddl q0, d4, d5 vmovl q1, d6 vmul q0, q0, q1 This allows us to vmull + vmlal for: f = vmull_u8( vget_high_u8(s), c); f = vmlal_u8(f, vget_low_u8(s), c); rdar://9197392 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128444 91177308-0d34-0410-b5e6-96231b3b80d8		2011-03-29 01:56:09 +00:00
..
Alpha
ARM	Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during	2011-03-29 01:56:09 +00:00
Blackfin	Be nice to Xcore and the XMOS assembler and avoid quoting section names	2011-03-04 20:03:14 +00:00
CBackend
CellSPU	Roll r127459 back in:	2011-03-11 21:52:04 +00:00
CPP
Generic	Make this test x86 specific because the ARM backend can't handle it.	2011-02-28 12:30:47 +00:00
MBlaze
Mips	Revert "Re-enable test and hope to silence the buildbots", still broken.	2011-03-09 22:48:46 +00:00
MSP430
PowerPC	Fix mistyped CHECK lines.	2011-03-09 22:07:31 +00:00
PTX	ptx: add analyze/insert/remove branch	2011-03-22 14:12:00 +00:00
SPARC
SystemZ
Thumb	Roll r127459 back in:	2011-03-11 21:52:04 +00:00
Thumb2	Fix the bfi handling for or (and a mask) (and b mask). We need the two	2011-03-26 01:21:03 +00:00
X86	In some cases, the "fail BB dominator" may be null after the BB was split (and	2011-03-28 23:02:18 +00:00
XCore	Add XCore intrinsic for setpsc.	2011-03-17 18:42:05 +00:00