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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34596 91177308-0d34-0410-b5e6-96231b3b80d8
149 lines
4.8 KiB
C++
149 lines
4.8 KiB
C++
//===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the Evan Cheng and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the machine register scavenger. It can provide
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// information such as unused register at any point in a machine basic block.
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// It also provides a mechanism to make registers availbale by evicting them
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// to spill slots.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reg-scavenging"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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RegScavenger::RegScavenger(MachineBasicBlock *mbb)
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: MBB(mbb), MBBI(mbb->begin()) {
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const MachineFunction &MF = *MBB->getParent();
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo *RegInfo = TM.getRegisterInfo();
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NumPhysRegs = RegInfo->getNumRegs();
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RegStates.resize(NumPhysRegs, true);
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// Create reserved registers bitvector.
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ReservedRegs = RegInfo->getReservedRegs(MF);
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RegStates ^= ReservedRegs;
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// Create callee-saved registers bitvector.
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CalleeSavedRegs.resize(NumPhysRegs);
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const unsigned *CSRegs = RegInfo->getCalleeSavedRegs();
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if (CSRegs != NULL)
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for (unsigned i = 0; CSRegs[i]; ++i)
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CalleeSavedRegs.set(CSRegs[i]);
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// Live-in registers are in use.
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if (!MBB->livein_empty())
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for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
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E = MBB->livein_end(); I != E; ++I)
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setUsed(*I);
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}
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void RegScavenger::forward() {
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MachineInstr *MI = MBBI;
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// Process uses first.
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BitVector ChangedRegs(NumPhysRegs);
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0)
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continue;
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assert(isUsed(Reg));
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if (MO.isKill() && !isReserved(Reg))
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ChangedRegs.set(Reg);
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}
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// Change states of all registers after all the uses are processed to guard
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// against multiple uses.
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setUnused(ChangedRegs);
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// Process defs.
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const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef())
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continue;
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unsigned Reg = MO.getReg();
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// Skip two-address destination operand.
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if (TID->findTiedToSrcOperand(i) != -1) {
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assert(isUsed(Reg));
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continue;
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}
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assert(isUnused(Reg) || isReserved(Reg));
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if (!MO.isDead())
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setUsed(Reg);
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}
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++MBBI;
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}
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void RegScavenger::backward() {
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MachineInstr *MI = --MBBI;
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// Process defs first.
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const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef())
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continue;
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// Skip two-address destination operand.
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if (TID->findTiedToSrcOperand(i) != -1)
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continue;
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unsigned Reg = MO.getReg();
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assert(isUsed(Reg));
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if (!isReserved(Reg))
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setUnused(Reg);
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}
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// Process uses.
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BitVector ChangedRegs(NumPhysRegs);
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse())
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continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0)
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continue;
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assert(isUnused(Reg) || isReserved(Reg));
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ChangedRegs.set(Reg);
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}
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setUsed(ChangedRegs);
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}
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/// CreateRegClassMask - Set the bits that represent the registers in the
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/// TargetRegisterClass.
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static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
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for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
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++I)
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Mask.set(*I);
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}
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unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
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bool ExCalleeSaved) const {
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// Mask off the registers which are not in the TargetRegisterClass.
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BitVector RegStatesCopy(NumPhysRegs, false);
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CreateRegClassMask(RegClass, RegStatesCopy);
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RegStatesCopy &= RegStates;
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// If looking for a non-callee-saved register, mask off all the callee-saved
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// registers.
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if (ExCalleeSaved)
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RegStatesCopy &= ~CalleeSavedRegs;
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// Returns the first unused (bit is set) register, or 0 is none is found.
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int Reg = RegStatesCopy.find_first();
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return (Reg == -1) ? 0 : Reg;
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}
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