Nate Begeman 7973f350b7 Implement sdiv & udiv for <4 x i16> and <8 x i8> NEON vector types. ... This avoids moving each element to the integer register file and calling __divsi3 etc. on it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125402 91177308-0d34-0410-b5e6-96231b3b80d8		2011-02-11 20:53:29 +00:00
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Alpha
ARM	Implement sdiv & udiv for <4 x i16> and <8 x i8> NEON vector types.	2011-02-11 20:53:29 +00:00
Blackfin
CBackend
CellSPU	Allow sign-extending of i8 and i16 to i128 on SPU.	2011-01-20 15:49:06 +00:00
CPP
Generic	fix rdar://8878965, a regression I introduced with the recent	2011-01-18 20:53:04 +00:00
MBlaze
Mips	Disable this test for now...	2011-02-11 02:59:08 +00:00
MSP430
PowerPC
PTX	ptx: add passing parameter to kernel functions	2011-02-10 12:01:24 +00:00
SPARC	Pass sret arguments through the stack instead of through registers in Sparc backend. It makes the code generated more compliant with the sparc32 ABI.	2011-01-22 13:05:16 +00:00
SystemZ
Thumb	Sorry, several patches in one.	2011-01-20 08:34:58 +00:00
Thumb2	Move a test that ended up in the wrong place.	2011-02-05 04:15:50 +00:00
X86	After 3-addressifying a two-address instruction, update the register maps; add a missing check when considering whether it's profitable to commute. rdar://8977508.	2011-02-10 02:20:55 +00:00
XCore	Add intrinsic for setc instruction on the XCore.	2011-02-09 13:22:12 +00:00