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https://github.com/c64scene-ar/llvm-6502.git
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2a9d1ca9c2
The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| .. | ||
| TargetInfo | ||
| CMakeLists.txt | ||
| Makefile | ||
| README.txt | ||
| XCore.h | ||
| XCore.td | ||
| XCoreAsmPrinter.cpp | ||
| XCoreCallingConv.td | ||
| XCoreFrameLowering.cpp | ||
| XCoreFrameLowering.h | ||
| XCoreInstrFormats.td | ||
| XCoreInstrInfo.cpp | ||
| XCoreInstrInfo.h | ||
| XCoreInstrInfo.td | ||
| XCoreISelDAGToDAG.cpp | ||
| XCoreISelLowering.cpp | ||
| XCoreISelLowering.h | ||
| XCoreMachineFunctionInfo.h | ||
| XCoreMCAsmInfo.cpp | ||
| XCoreMCAsmInfo.h | ||
| XCoreRegisterInfo.cpp | ||
| XCoreRegisterInfo.h | ||
| XCoreRegisterInfo.td | ||
| XCoreSelectionDAGInfo.cpp | ||
| XCoreSelectionDAGInfo.h | ||
| XCoreSubtarget.cpp | ||
| XCoreSubtarget.h | ||
| XCoreTargetMachine.cpp | ||
| XCoreTargetMachine.h | ||
| XCoreTargetObjectFile.cpp | ||
| XCoreTargetObjectFile.h | ||
To-do ----- * Instruction encodings * Tailcalls * Investigate loop alignment * Add builtins