llvm-6502/test/CodeGen
2015-02-18 18:31:51 +00:00
..
AArch64 AArch64: Safely handle the incoming sret call argument. 2015-02-16 18:10:47 +00:00
ARM [ARM] Add missing M/R class CPUs 2015-02-18 10:33:30 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator 2015-02-18 17:33:56 +00:00
MSP430
NVPTX
PowerPC This patch adds the VSX logical instructions introduced in the Power ISA 2.07. It also removes the added complexity that favors VMX versions of the three instructions. 2015-02-18 16:21:46 +00:00
R600 R600/SI: Add missing offset operand to buffer bothen 2015-02-18 02:04:38 +00:00
SPARC SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too 2015-02-16 21:47:58 +00:00
SystemZ [SystemZ] Support all TLS access models - CodeGen part 2015-02-18 09:13:27 +00:00
Thumb
Thumb2
X86 Adding implementation to outline C++ catch handlers for native Windows 64 exception handling. 2015-02-18 18:31:51 +00:00
XCore