Jakob Stoklund Olesen c02a6fa7d8 Don't use register classes larger than TLI->getRegClassFor(VT). ... In Thumb mode we cannot handle GPR virtual registers, even though some instructions can. When isel is lowering a CopyFromReg, it should limit itself to subclasses of getRegClassFor(VT). <rdar://problem/9624323> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133210 91177308-0d34-0410-b5e6-96231b3b80d8		2011-06-16 22:50:38 +00:00
..
CMakeLists.txt
DAGCombiner.cpp	Add a DAGCombine for (ext (binop (load x), cst)).	2011-06-16 01:15:49 +00:00
FastISel.cpp	PR10077: fix fast-isel of extractvalue of aggregate constants.	2011-06-06 05:46:34 +00:00
FunctionLoweringInfo.cpp	Add a parameter to CCState so that it can access the MachineFunction.	2011-06-08 23:55:35 +00:00
InstrEmitter.cpp	Don't use register classes larger than TLI->getRegClassFor(VT).	2011-06-16 22:50:38 +00:00
InstrEmitter.h
LegalizeDAG.cpp	Add a testcase for checking the integer-promotion of many different vector	2011-06-14 08:11:52 +00:00
LegalizeFloatTypes.cpp
LegalizeIntegerTypes.cpp	getZeroExtendInReg needs to get a scalar type	2011-06-15 14:37:18 +00:00
LegalizeTypes.cpp	Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer use	2011-06-01 19:47:10 +00:00
LegalizeTypes.h	Enable the simplification of truncating-store after fixing the usage of	2011-06-15 11:19:12 +00:00
LegalizeTypesGeneric.cpp	Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer use	2011-06-01 19:47:10 +00:00
LegalizeVectorOps.cpp
LegalizeVectorTypes.cpp	Fix a bug in FindMemType. When widening vector loads, use a wider memory type	2011-06-13 18:13:24 +00:00
Makefile
ScheduleDAGFast.cpp
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp	Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.	2011-06-15 23:35:18 +00:00
ScheduleDAGSDNodes.cpp	Added -stress-sched flag in the Asserts build.	2011-06-15 17:16:12 +00:00
ScheduleDAGSDNodes.h	Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match.	2011-06-15 23:35:18 +00:00
SDNodeDbgValue.h
SDNodeOrdering.h
SelectionDAG.cpp
SelectionDAGBuilder.cpp	Introduce MachineBranchProbabilityInfo class, which has similar API to	2011-06-16 20:22:37 +00:00
SelectionDAGBuilder.h	Introduce MachineBranchProbabilityInfo class, which has similar API to	2011-06-16 20:22:37 +00:00
SelectionDAGISel.cpp	Introduce MachineBranchProbabilityInfo class, which has similar API to	2011-06-16 20:22:37 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp	Fix a bug in the calculation of the vectorTypeBreakdown into registers. Odd	2011-06-12 14:56:55 +00:00
TargetSelectionDAGInfo.cpp