llvm-6502/test/CodeGen
Ulrich Weigand 33efedc048 [PowerPC] Use mtocrf when available
Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.

Current code however always emits mtcrf.  This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible.  It does create
inefficient code with the integrated assembler, however.

To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything.  Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.

As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-03 17:59:07 +00:00
..
AArch64 AArch64: correct CodeGen of MOVZ/MOVK combinations. 2013-07-01 19:23:10 +00:00
ARM Prefix failing commands with not to make clear they are expected to fail. 2013-07-03 16:41:29 +00:00
CPP
Generic Debug Info: clean up usage of Verify. 2013-06-28 05:43:10 +00:00
Hexagon Hexagon: Pass to replace tranfer/copy instructions into combine instruction 2013-05-14 18:54:06 +00:00
Inputs
MBlaze
Mips [mips] Fix test case to check that mips64 instructions are generated. 2013-07-01 20:18:58 +00:00
MSP430 Really fix the test. Sorry for the breakage... 2013-07-01 19:51:36 +00:00
NVPTX [NVPTX] Add support for module-scope inline asm 2013-07-01 13:00:14 +00:00
PowerPC [PowerPC] Use mtocrf when available 2013-07-03 17:59:07 +00:00
R600 Prefix failing commands with not to make clear they are expected to fail. 2013-07-03 16:41:29 +00:00
SI
SPARC Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo. 2013-06-17 19:00:36 +00:00
SystemZ [SystemZ] Fold more spills 2013-07-03 10:10:02 +00:00
Thumb
Thumb2 ARM: allow predicated barriers in Thumb mode 2013-06-26 16:52:32 +00:00
X86 Prefix failing commands with not to make clear they are expected to fail. 2013-07-03 16:41:29 +00:00
XCore [XCore] Add ISel pattern for LDWCP 2013-07-03 07:48:50 +00:00