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c6af2432c8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
669 lines
22 KiB
C++
669 lines
22 KiB
C++
//===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM addressing mode implementation stuff.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
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#define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include <cassert>
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namespace llvm {
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/// ARM_AM - ARM Addressing Mode Stuff
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namespace ARM_AM {
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enum ShiftOpc {
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no_shift = 0,
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asr,
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lsl,
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lsr,
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ror,
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rrx
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};
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enum AddrOpc {
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sub = 0,
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add
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};
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static inline const char *getAddrOpcStr(AddrOpc Op) {
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return Op == sub ? "-" : "";
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}
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static inline const char *getShiftOpcStr(ShiftOpc Op) {
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switch (Op) {
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default: llvm_unreachable("Unknown shift opc!");
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case ARM_AM::asr: return "asr";
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case ARM_AM::lsl: return "lsl";
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case ARM_AM::lsr: return "lsr";
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case ARM_AM::ror: return "ror";
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case ARM_AM::rrx: return "rrx";
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}
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}
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static inline unsigned getShiftOpcEncoding(ShiftOpc Op) {
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switch (Op) {
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default: llvm_unreachable("Unknown shift opc!");
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case ARM_AM::asr: return 2;
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case ARM_AM::lsl: return 0;
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case ARM_AM::lsr: return 1;
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case ARM_AM::ror: return 3;
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}
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}
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enum AMSubMode {
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bad_am_submode = 0,
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ia,
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ib,
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da,
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db
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};
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static inline const char *getAMSubModeStr(AMSubMode Mode) {
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switch (Mode) {
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default: llvm_unreachable("Unknown addressing sub-mode!");
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case ARM_AM::ia: return "ia";
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case ARM_AM::ib: return "ib";
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case ARM_AM::da: return "da";
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case ARM_AM::db: return "db";
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}
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}
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/// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
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///
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static inline unsigned rotr32(unsigned Val, unsigned Amt) {
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assert(Amt < 32 && "Invalid rotate amount");
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return (Val >> Amt) | (Val << ((32-Amt)&31));
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}
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/// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
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///
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static inline unsigned rotl32(unsigned Val, unsigned Amt) {
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assert(Amt < 32 && "Invalid rotate amount");
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return (Val << Amt) | (Val >> ((32-Amt)&31));
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #1: shift_operand with registers
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//===--------------------------------------------------------------------===//
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//
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// This 'addressing mode' is used for arithmetic instructions. It can
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// represent things like:
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// reg
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// reg [asr|lsl|lsr|ror|rrx] reg
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// reg [asr|lsl|lsr|ror|rrx] imm
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//
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// This is stored three operands [rega, regb, opc]. The first is the base
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// reg, the second is the shift amount (or reg0 if not present or imm). The
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// third operand encodes the shift opcode and the imm if a reg isn't present.
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//
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static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
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return ShOp | (Imm << 3);
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}
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static inline unsigned getSORegOffset(unsigned Op) {
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return Op >> 3;
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}
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static inline ShiftOpc getSORegShOp(unsigned Op) {
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return (ShiftOpc)(Op & 7);
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}
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/// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
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/// the 8-bit imm value.
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static inline unsigned getSOImmValImm(unsigned Imm) {
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return Imm & 0xFF;
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}
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/// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
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/// the rotate amount.
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static inline unsigned getSOImmValRot(unsigned Imm) {
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return (Imm >> 8) * 2;
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}
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/// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
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/// computing the rotate amount to use. If this immediate value cannot be
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/// handled with a single shifter-op, determine a good rotate amount that will
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/// take a maximal chunk of bits out of the immediate.
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static inline unsigned getSOImmValRotate(unsigned Imm) {
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// 8-bit (or less) immediates are trivially shifter_operands with a rotate
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// of zero.
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if ((Imm & ~255U) == 0) return 0;
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// Use CTZ to compute the rotate amount.
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unsigned TZ = countTrailingZeros(Imm);
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// Rotate amount must be even. Something like 0x200 must be rotated 8 bits,
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// not 9.
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unsigned RotAmt = TZ & ~1;
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// If we can handle this spread, return it.
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if ((rotr32(Imm, RotAmt) & ~255U) == 0)
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return (32-RotAmt)&31; // HW rotates right, not left.
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// For values like 0xF000000F, we should ignore the low 6 bits, then
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// retry the hunt.
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if (Imm & 63U) {
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unsigned TZ2 = countTrailingZeros(Imm & ~63U);
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unsigned RotAmt2 = TZ2 & ~1;
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if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
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return (32-RotAmt2)&31; // HW rotates right, not left.
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}
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// Otherwise, we have no way to cover this span of bits with a single
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// shifter_op immediate. Return a chunk of bits that will be useful to
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// handle.
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return (32-RotAmt)&31; // HW rotates right, not left.
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}
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/// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
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/// into an shifter_operand immediate operand, return the 12-bit encoding for
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/// it. If not, return -1.
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static inline int getSOImmVal(unsigned Arg) {
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// 8-bit (or less) immediates are trivially shifter_operands with a rotate
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// of zero.
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if ((Arg & ~255U) == 0) return Arg;
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unsigned RotAmt = getSOImmValRotate(Arg);
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// If this cannot be handled with a single shifter_op, bail out.
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if (rotr32(~255U, RotAmt) & Arg)
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return -1;
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// Encode this correctly.
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return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
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}
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/// isSOImmTwoPartVal - Return true if the specified value can be obtained by
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/// or'ing together two SOImmVal's.
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static inline bool isSOImmTwoPartVal(unsigned V) {
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// If this can be handled with a single shifter_op, bail out.
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V = rotr32(~255U, getSOImmValRotate(V)) & V;
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if (V == 0)
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return false;
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// If this can be handled with two shifter_op's, accept.
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V = rotr32(~255U, getSOImmValRotate(V)) & V;
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return V == 0;
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}
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/// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
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/// return the first chunk of it.
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static inline unsigned getSOImmTwoPartFirst(unsigned V) {
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return rotr32(255U, getSOImmValRotate(V)) & V;
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}
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/// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
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/// return the second chunk of it.
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static inline unsigned getSOImmTwoPartSecond(unsigned V) {
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// Mask out the first hunk.
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V = rotr32(~255U, getSOImmValRotate(V)) & V;
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// Take what's left.
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assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
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return V;
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}
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/// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
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/// by a left shift. Returns the shift amount to use.
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static inline unsigned getThumbImmValShift(unsigned Imm) {
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// 8-bit (or less) immediates are trivially immediate operand with a shift
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// of zero.
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if ((Imm & ~255U) == 0) return 0;
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// Use CTZ to compute the shift amount.
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return countTrailingZeros(Imm);
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}
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/// isThumbImmShiftedVal - Return true if the specified value can be obtained
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/// by left shifting a 8-bit immediate.
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static inline bool isThumbImmShiftedVal(unsigned V) {
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// If this can be handled with
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V = (~255U << getThumbImmValShift(V)) & V;
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return V == 0;
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}
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/// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
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/// by a left shift. Returns the shift amount to use.
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static inline unsigned getThumbImm16ValShift(unsigned Imm) {
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// 16-bit (or less) immediates are trivially immediate operand with a shift
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// of zero.
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if ((Imm & ~65535U) == 0) return 0;
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// Use CTZ to compute the shift amount.
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return countTrailingZeros(Imm);
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}
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/// isThumbImm16ShiftedVal - Return true if the specified value can be
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/// obtained by left shifting a 16-bit immediate.
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static inline bool isThumbImm16ShiftedVal(unsigned V) {
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// If this can be handled with
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V = (~65535U << getThumbImm16ValShift(V)) & V;
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return V == 0;
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}
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/// getThumbImmNonShiftedVal - If V is a value that satisfies
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/// isThumbImmShiftedVal, return the non-shiftd value.
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static inline unsigned getThumbImmNonShiftedVal(unsigned V) {
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return V >> getThumbImmValShift(V);
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}
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/// getT2SOImmValSplat - Return the 12-bit encoded representation
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/// if the specified value can be obtained by splatting the low 8 bits
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/// into every other byte or every byte of a 32-bit value. i.e.,
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/// 00000000 00000000 00000000 abcdefgh control = 0
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/// 00000000 abcdefgh 00000000 abcdefgh control = 1
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/// abcdefgh 00000000 abcdefgh 00000000 control = 2
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/// abcdefgh abcdefgh abcdefgh abcdefgh control = 3
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/// Return -1 if none of the above apply.
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/// See ARM Reference Manual A6.3.2.
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static inline int getT2SOImmValSplatVal(unsigned V) {
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unsigned u, Vs, Imm;
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// control = 0
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if ((V & 0xffffff00) == 0)
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return V;
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// If the value is zeroes in the first byte, just shift those off
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Vs = ((V & 0xff) == 0) ? V >> 8 : V;
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// Any passing value only has 8 bits of payload, splatted across the word
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Imm = Vs & 0xff;
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// Likewise, any passing values have the payload splatted into the 3rd byte
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u = Imm | (Imm << 16);
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// control = 1 or 2
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if (Vs == u)
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return (((Vs == V) ? 1 : 2) << 8) | Imm;
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// control = 3
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if (Vs == (u | (u << 8)))
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return (3 << 8) | Imm;
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return -1;
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}
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/// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the
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/// specified value is a rotated 8-bit value. Return -1 if no rotation
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/// encoding is possible.
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/// See ARM Reference Manual A6.3.2.
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static inline int getT2SOImmValRotateVal(unsigned V) {
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unsigned RotAmt = countLeadingZeros(V);
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if (RotAmt >= 24)
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return -1;
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// If 'Arg' can be handled with a single shifter_op return the value.
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if ((rotr32(0xff000000U, RotAmt) & V) == V)
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return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
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return -1;
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}
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/// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
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/// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
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/// encoding for it. If not, return -1.
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/// See ARM Reference Manual A6.3.2.
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static inline int getT2SOImmVal(unsigned Arg) {
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// If 'Arg' is an 8-bit splat, then get the encoded value.
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int Splat = getT2SOImmValSplatVal(Arg);
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if (Splat != -1)
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return Splat;
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// If 'Arg' can be handled with a single shifter_op return the value.
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int Rot = getT2SOImmValRotateVal(Arg);
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if (Rot != -1)
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return Rot;
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return -1;
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}
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static inline unsigned getT2SOImmValRotate(unsigned V) {
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if ((V & ~255U) == 0) return 0;
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// Use CTZ to compute the rotate amount.
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unsigned RotAmt = countTrailingZeros(V);
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return (32 - RotAmt) & 31;
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}
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static inline bool isT2SOImmTwoPartVal (unsigned Imm) {
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unsigned V = Imm;
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// Passing values can be any combination of splat values and shifter
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// values. If this can be handled with a single shifter or splat, bail
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// out. Those should be handled directly, not with a two-part val.
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if (getT2SOImmValSplatVal(V) != -1)
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return false;
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V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
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if (V == 0)
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return false;
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// If this can be handled as an immediate, accept.
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if (getT2SOImmVal(V) != -1) return true;
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// Likewise, try masking out a splat value first.
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V = Imm;
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if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
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V &= ~0xff00ff00U;
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else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
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V &= ~0x00ff00ffU;
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// If what's left can be handled as an immediate, accept.
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if (getT2SOImmVal(V) != -1) return true;
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// Otherwise, do not accept.
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return false;
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}
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static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) {
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assert (isT2SOImmTwoPartVal(Imm) &&
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"Immedate cannot be encoded as two part immediate!");
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// Try a shifter operand as one part
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unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;
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// If the rest is encodable as an immediate, then return it.
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if (getT2SOImmVal(V) != -1) return V;
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// Try masking out a splat value first.
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if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
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return Imm & 0xff00ff00U;
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// The other splat is all that's left as an option.
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assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
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return Imm & 0x00ff00ffU;
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}
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static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) {
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// Mask out the first hunk
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Imm ^= getT2SOImmTwoPartFirst(Imm);
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// Return what's left
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assert (getT2SOImmVal(Imm) != -1 &&
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"Unable to encode second part of T2 two part SO immediate");
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return Imm;
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #2
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//===--------------------------------------------------------------------===//
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//
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// This is used for most simple load/store instructions.
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//
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// addrmode2 := reg +/- reg shop imm
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// addrmode2 := reg +/- imm12
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//
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// The first operand is always a Reg. The second operand is a reg if in
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// reg/reg form, otherwise it's reg#0. The third field encodes the operation
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// in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
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// fourth operand 16-17 encodes the index mode.
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//
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// If this addressing mode is a frame index (before prolog/epilog insertion
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// and code rewriting), this operand will have the form: FI#, reg0, <offs>
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// with no shift amount for the frame offset.
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//
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static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
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unsigned IdxMode = 0) {
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assert(Imm12 < (1 << 12) && "Imm too large!");
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bool isSub = Opc == sub;
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return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
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}
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static inline unsigned getAM2Offset(unsigned AM2Opc) {
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return AM2Opc & ((1 << 12)-1);
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}
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static inline AddrOpc getAM2Op(unsigned AM2Opc) {
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return ((AM2Opc >> 12) & 1) ? sub : add;
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}
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static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
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return (ShiftOpc)((AM2Opc >> 13) & 7);
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}
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static inline unsigned getAM2IdxMode(unsigned AM2Opc) {
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return (AM2Opc >> 16);
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #3
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//===--------------------------------------------------------------------===//
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//
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// This is used for sign-extending loads, and load/store-pair instructions.
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//
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// addrmode3 := reg +/- reg
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// addrmode3 := reg +/- imm8
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//
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// The first operand is always a Reg. The second operand is a reg if in
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// reg/reg form, otherwise it's reg#0. The third field encodes the operation
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// in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
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// index mode.
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/// getAM3Opc - This function encodes the addrmode3 opc field.
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static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
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unsigned IdxMode = 0) {
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bool isSub = Opc == sub;
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return ((int)isSub << 8) | Offset | (IdxMode << 9);
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}
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static inline unsigned char getAM3Offset(unsigned AM3Opc) {
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return AM3Opc & 0xFF;
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}
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static inline AddrOpc getAM3Op(unsigned AM3Opc) {
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return ((AM3Opc >> 8) & 1) ? sub : add;
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}
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static inline unsigned getAM3IdxMode(unsigned AM3Opc) {
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return (AM3Opc >> 9);
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #4
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//===--------------------------------------------------------------------===//
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//
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// This is used for load / store multiple instructions.
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//
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// addrmode4 := reg, <mode>
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//
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// The four modes are:
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// IA - Increment after
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// IB - Increment before
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// DA - Decrement after
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// DB - Decrement before
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// For VFP instructions, only the IA and DB modes are valid.
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static inline AMSubMode getAM4SubMode(unsigned Mode) {
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return (AMSubMode)(Mode & 0x7);
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}
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static inline unsigned getAM4ModeImm(AMSubMode SubMode) {
|
|
return (int)SubMode;
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Addressing Mode #5
|
|
//===--------------------------------------------------------------------===//
|
|
//
|
|
// This is used for coprocessor instructions, such as FP load/stores.
|
|
//
|
|
// addrmode5 := reg +/- imm8*4
|
|
//
|
|
// The first operand is always a Reg. The second operand encodes the
|
|
// operation in bit 8 and the immediate in bits 0-7.
|
|
|
|
/// getAM5Opc - This function encodes the addrmode5 opc field.
|
|
static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
|
|
bool isSub = Opc == sub;
|
|
return ((int)isSub << 8) | Offset;
|
|
}
|
|
static inline unsigned char getAM5Offset(unsigned AM5Opc) {
|
|
return AM5Opc & 0xFF;
|
|
}
|
|
static inline AddrOpc getAM5Op(unsigned AM5Opc) {
|
|
return ((AM5Opc >> 8) & 1) ? sub : add;
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Addressing Mode #6
|
|
//===--------------------------------------------------------------------===//
|
|
//
|
|
// This is used for NEON load / store instructions.
|
|
//
|
|
// addrmode6 := reg with optional alignment
|
|
//
|
|
// This is stored in two operands [regaddr, align]. The first is the
|
|
// address register. The second operand is the value of the alignment
|
|
// specifier in bytes or zero if no explicit alignment.
|
|
// Valid alignments depend on the specific instruction.
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// NEON Modified Immediates
|
|
//===--------------------------------------------------------------------===//
|
|
//
|
|
// Several NEON instructions (e.g., VMOV) take a "modified immediate"
|
|
// vector operand, where a small immediate encoded in the instruction
|
|
// specifies a full NEON vector value. These modified immediates are
|
|
// represented here as encoded integers. The low 8 bits hold the immediate
|
|
// value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
|
|
// the "Cmode" field of the instruction. The interfaces below treat the
|
|
// Op and Cmode values as a single 5-bit value.
|
|
|
|
static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) {
|
|
return (OpCmode << 8) | Val;
|
|
}
|
|
static inline unsigned getNEONModImmOpCmode(unsigned ModImm) {
|
|
return (ModImm >> 8) & 0x1f;
|
|
}
|
|
static inline unsigned getNEONModImmVal(unsigned ModImm) {
|
|
return ModImm & 0xff;
|
|
}
|
|
|
|
/// decodeNEONModImm - Decode a NEON modified immediate value into the
|
|
/// element value and the element size in bits. (If the element size is
|
|
/// smaller than the vector, it is splatted into all the elements.)
|
|
static inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) {
|
|
unsigned OpCmode = getNEONModImmOpCmode(ModImm);
|
|
unsigned Imm8 = getNEONModImmVal(ModImm);
|
|
uint64_t Val = 0;
|
|
|
|
if (OpCmode == 0xe) {
|
|
// 8-bit vector elements
|
|
Val = Imm8;
|
|
EltBits = 8;
|
|
} else if ((OpCmode & 0xc) == 0x8) {
|
|
// 16-bit vector elements
|
|
unsigned ByteNum = (OpCmode & 0x6) >> 1;
|
|
Val = Imm8 << (8 * ByteNum);
|
|
EltBits = 16;
|
|
} else if ((OpCmode & 0x8) == 0) {
|
|
// 32-bit vector elements, zero with one byte set
|
|
unsigned ByteNum = (OpCmode & 0x6) >> 1;
|
|
Val = Imm8 << (8 * ByteNum);
|
|
EltBits = 32;
|
|
} else if ((OpCmode & 0xe) == 0xc) {
|
|
// 32-bit vector elements, one byte with low bits set
|
|
unsigned ByteNum = 1 + (OpCmode & 0x1);
|
|
Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
|
|
EltBits = 32;
|
|
} else if (OpCmode == 0x1e) {
|
|
// 64-bit vector elements
|
|
for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
|
|
if ((ModImm >> ByteNum) & 1)
|
|
Val |= (uint64_t)0xff << (8 * ByteNum);
|
|
}
|
|
EltBits = 64;
|
|
} else {
|
|
llvm_unreachable("Unsupported NEON immediate");
|
|
}
|
|
return Val;
|
|
}
|
|
|
|
AMSubMode getLoadStoreMultipleSubMode(int Opcode);
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// Floating-point Immediates
|
|
//
|
|
static inline float getFPImmFloat(unsigned Imm) {
|
|
// We expect an 8-bit binary encoding of a floating-point number here.
|
|
union {
|
|
uint32_t I;
|
|
float F;
|
|
} FPUnion;
|
|
|
|
uint8_t Sign = (Imm >> 7) & 0x1;
|
|
uint8_t Exp = (Imm >> 4) & 0x7;
|
|
uint8_t Mantissa = Imm & 0xf;
|
|
|
|
// 8-bit FP iEEEE Float Encoding
|
|
// abcd efgh aBbbbbbc defgh000 00000000 00000000
|
|
//
|
|
// where B = NOT(b);
|
|
|
|
FPUnion.I = 0;
|
|
FPUnion.I |= Sign << 31;
|
|
FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
|
|
FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
|
|
FPUnion.I |= (Exp & 0x3) << 23;
|
|
FPUnion.I |= Mantissa << 19;
|
|
return FPUnion.F;
|
|
}
|
|
|
|
/// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
|
|
/// floating-point value. If the value cannot be represented as an 8-bit
|
|
/// floating-point value, then return -1.
|
|
static inline int getFP32Imm(const APInt &Imm) {
|
|
uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
|
|
int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
|
|
int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
|
|
|
|
// We can handle 4 bits of mantissa.
|
|
// mantissa = (16+UInt(e:f:g:h))/16.
|
|
if (Mantissa & 0x7ffff)
|
|
return -1;
|
|
Mantissa >>= 19;
|
|
if ((Mantissa & 0xf) != Mantissa)
|
|
return -1;
|
|
|
|
// We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
|
|
if (Exp < -3 || Exp > 4)
|
|
return -1;
|
|
Exp = ((Exp+3) & 0x7) ^ 4;
|
|
|
|
return ((int)Sign << 7) | (Exp << 4) | Mantissa;
|
|
}
|
|
|
|
static inline int getFP32Imm(const APFloat &FPImm) {
|
|
return getFP32Imm(FPImm.bitcastToAPInt());
|
|
}
|
|
|
|
/// getFP64Imm - Return an 8-bit floating-point version of the 64-bit
|
|
/// floating-point value. If the value cannot be represented as an 8-bit
|
|
/// floating-point value, then return -1.
|
|
static inline int getFP64Imm(const APInt &Imm) {
|
|
uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
|
|
int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
|
|
uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;
|
|
|
|
// We can handle 4 bits of mantissa.
|
|
// mantissa = (16+UInt(e:f:g:h))/16.
|
|
if (Mantissa & 0xffffffffffffULL)
|
|
return -1;
|
|
Mantissa >>= 48;
|
|
if ((Mantissa & 0xf) != Mantissa)
|
|
return -1;
|
|
|
|
// We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
|
|
if (Exp < -3 || Exp > 4)
|
|
return -1;
|
|
Exp = ((Exp+3) & 0x7) ^ 4;
|
|
|
|
return ((int)Sign << 7) | (Exp << 4) | Mantissa;
|
|
}
|
|
|
|
static inline int getFP64Imm(const APFloat &FPImm) {
|
|
return getFP64Imm(FPImm.bitcastToAPInt());
|
|
}
|
|
|
|
} // end namespace ARM_AM
|
|
} // end namespace llvm
|
|
|
|
#endif
|
|
|