mirror of
https://github.com/c64scene-ar/llvm-6502.git
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09e28e39f0
This patch implements a few changes related to the Thumb2 M-class MSR instruction: * better handling of unpredictable encodings, * recognition of the _g and _nzcvqg variants by the asm parser only if the DSP extension is available, preferred output of MSR APSR moves with the _<bits> suffix for v7-M. Patch by Petr Pavlu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216874 91177308-0d34-0410-b5e6-96231b3b80d8
80 lines
3.7 KiB
ArmAsm
80 lines
3.7 KiB
ArmAsm
@ RUN: llvm-mc -triple=thumbv6m -show-encoding < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V6M %s
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@ RUN: llvm-mc -triple=thumbv7m -show-encoding < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
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.syntax unified
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@ Check that the assembler can handle the documented syntax from the ARM ARM.
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@ These tests test instruction encodings specific to v6m & v7m (FeatureMClass).
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@------------------------------------------------------------------------------
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@ MRS
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@------------------------------------------------------------------------------
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mrs r0, apsr
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mrs r0, iapsr
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mrs r0, eapsr
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mrs r0, xpsr
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mrs r0, ipsr
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mrs r0, epsr
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mrs r0, iepsr
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mrs r0, msp
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mrs r0, psp
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mrs r0, primask
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mrs r0, control
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@ CHECK: mrs r0, apsr @ encoding: [0xef,0xf3,0x00,0x80]
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@ CHECK: mrs r0, iapsr @ encoding: [0xef,0xf3,0x01,0x80]
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@ CHECK: mrs r0, eapsr @ encoding: [0xef,0xf3,0x02,0x80]
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@ CHECK: mrs r0, xpsr @ encoding: [0xef,0xf3,0x03,0x80]
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@ CHECK: mrs r0, ipsr @ encoding: [0xef,0xf3,0x05,0x80]
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@ CHECK: mrs r0, epsr @ encoding: [0xef,0xf3,0x06,0x80]
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@ CHECK: mrs r0, iepsr @ encoding: [0xef,0xf3,0x07,0x80]
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@ CHECK: mrs r0, msp @ encoding: [0xef,0xf3,0x08,0x80]
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@ CHECK: mrs r0, psp @ encoding: [0xef,0xf3,0x09,0x80]
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@ CHECK: mrs r0, primask @ encoding: [0xef,0xf3,0x10,0x80]
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@ CHECK: mrs r0, control @ encoding: [0xef,0xf3,0x14,0x80]
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@------------------------------------------------------------------------------
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@ MSR
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@------------------------------------------------------------------------------
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msr apsr, r0
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msr apsr_nzcvq, r0
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msr iapsr, r0
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msr iapsr_nzcvq, r0
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msr eapsr, r0
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msr eapsr_nzcvq, r0
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msr xpsr, r0
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msr xpsr_nzcvq, r0
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msr ipsr, r0
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msr epsr, r0
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msr iepsr, r0
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msr msp, r0
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msr psp, r0
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msr primask, r0
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msr control, r0
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@ CHECK-V6M: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88]
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@ CHECK-V6M: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88]
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@ CHECK-V6M: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88]
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@ CHECK-V6M: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88]
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@ CHECK-V6M: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88]
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@ CHECK-V6M: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88]
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@ CHECK-V6M: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88]
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@ CHECK-V6M: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88]
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@ CHECK-V7M: msr apsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x00,0x88]
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@ CHECK-V7M: msr apsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x00,0x88]
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@ CHECK-V7M: msr iapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x01,0x88]
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@ CHECK-V7M: msr iapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x01,0x88]
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@ CHECK-V7M: msr eapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x02,0x88]
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@ CHECK-V7M: msr eapsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x02,0x88]
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@ CHECK-V7M: msr xpsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x03,0x88]
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@ CHECK-V7M: msr xpsr_nzcvq, r0 @ encoding: [0x80,0xf3,0x03,0x88]
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@ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88]
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@ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x88]
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@ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x88]
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@ CHECK: msr msp, r0 @ encoding: [0x80,0xf3,0x08,0x88]
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@ CHECK: msr psp, r0 @ encoding: [0x80,0xf3,0x09,0x88]
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@ CHECK: msr primask, r0 @ encoding: [0x80,0xf3,0x10,0x88]
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@ CHECK: msr control, r0 @ encoding: [0x80,0xf3,0x14,0x88]
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