mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-05 13:29:22 +00:00
09e28e39f0
This patch implements a few changes related to the Thumb2 M-class MSR instruction: * better handling of unpredictable encodings, * recognition of the _g and _nzcvqg variants by the asm parser only if the DSP extension is available, preferred output of MSR APSR moves with the _<bits> suffix for v7-M. Patch by Petr Pavlu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216874 91177308-0d34-0410-b5e6-96231b3b80d8
54 lines
2.3 KiB
ArmAsm
54 lines
2.3 KiB
ArmAsm
@ RUN: llvm-mc -triple=thumbv7em -show-encoding < %s | FileCheck %s
|
|
@ RUN: not llvm-mc -triple=thumbv7m -show-encoding 2>&1 < %s | FileCheck --check-prefix=CHECK-V7M %s
|
|
|
|
.syntax unified
|
|
|
|
@ Check that the assembler can handle the documented syntax from the ARM ARM.
|
|
@ These tests test instruction encodings specific to ARMv7E-M.
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ MSR
|
|
@------------------------------------------------------------------------------
|
|
|
|
msr apsr_g, r0
|
|
msr apsr_nzcvqg, r0
|
|
msr iapsr_g, r0
|
|
msr iapsr_nzcvqg, r0
|
|
msr eapsr_g, r0
|
|
msr eapsr_nzcvqg, r0
|
|
msr xpsr_g, r0
|
|
msr xpsr_nzcvqg, r0
|
|
|
|
@ CHECK: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84]
|
|
@ CHECK: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c]
|
|
@ CHECK: msr iapsr_g, r0 @ encoding: [0x80,0xf3,0x01,0x84]
|
|
@ CHECK: msr iapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x01,0x8c]
|
|
@ CHECK: msr eapsr_g, r0 @ encoding: [0x80,0xf3,0x02,0x84]
|
|
@ CHECK: msr eapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x02,0x8c]
|
|
@ CHECK: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84]
|
|
@ CHECK: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c]
|
|
@ CHECK-V7M: error: invalid operand for instruction
|
|
@ CHECK-V7M-NEXT: msr apsr_g, r0
|
|
@ CHECK-V7M-NEXT: ^
|
|
@ CHECK-V7M: error: invalid operand for instruction
|
|
@ CHECK-V7M-NEXT: msr apsr_nzcvqg, r0
|
|
@ CHECK-V7M-NEXT: ^
|
|
@ CHECK-V7M: error: invalid operand for instruction
|
|
@ CHECK-V7M-NEXT: msr iapsr_g, r0
|
|
@ CHECK-V7M-NEXT: ^
|
|
@ CHECK-V7M: error: invalid operand for instruction
|
|
@ CHECK-V7M-NEXT: msr iapsr_nzcvqg, r0
|
|
@ CHECK-V7M-NEXT: ^
|
|
@ CHECK-V7M: error: invalid operand for instruction
|
|
@ CHECK-V7M-NEXT: msr eapsr_g, r0
|
|
@ CHECK-V7M-NEXT: ^
|
|
@ CHECK-V7M: error: invalid operand for instruction
|
|
@ CHECK-V7M-NEXT: msr eapsr_nzcvqg, r0
|
|
@ CHECK-V7M-NEXT: ^
|
|
@ CHECK-V7M: error: invalid operand for instruction
|
|
@ CHECK-V7M-NEXT: msr xpsr_g, r0
|
|
@ CHECK-V7M-NEXT: ^
|
|
@ CHECK-V7M: error: invalid operand for instruction
|
|
@ CHECK-V7M-NEXT: msr xpsr_nzcvqg, r0
|
|
@ CHECK-V7M-NEXT: ^
|