mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42153 91177308-0d34-0410-b5e6-96231b3b80d8
772 lines
26 KiB
C++
772 lines
26 KiB
C++
//===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ----*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Evan Cheng and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that performs load / store related peephole
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// optimizations. This pass should be run after register allocation.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "arm-ldst-opt"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMRegisterInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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STATISTIC(NumLDMGened , "Number of ldm instructions generated");
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STATISTIC(NumSTMGened , "Number of stm instructions generated");
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STATISTIC(NumFLDMGened, "Number of fldm instructions generated");
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STATISTIC(NumFSTMGened, "Number of fstm instructions generated");
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namespace {
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struct VISIBILITY_HIDDEN ARMLoadStoreOpt : public MachineFunctionPass {
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static char ID;
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ARMLoadStoreOpt() : MachineFunctionPass((intptr_t)&ID) {}
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const TargetInstrInfo *TII;
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const MRegisterInfo *MRI;
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ARMFunctionInfo *AFI;
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RegScavenger *RS;
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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virtual const char *getPassName() const {
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return "ARM load / store optimization pass";
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}
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private:
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struct MemOpQueueEntry {
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int Offset;
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unsigned Position;
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MachineBasicBlock::iterator MBBI;
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bool Merged;
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MemOpQueueEntry(int o, int p, MachineBasicBlock::iterator i)
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: Offset(o), Position(p), MBBI(i), Merged(false) {};
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};
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typedef SmallVector<MemOpQueueEntry,8> MemOpQueue;
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typedef MemOpQueue::iterator MemOpQueueIter;
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SmallVector<MachineBasicBlock::iterator, 4>
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MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
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int Opcode, unsigned Size,
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ARMCC::CondCodes Pred, unsigned PredReg,
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unsigned Scratch, MemOpQueue &MemOps);
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void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
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bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
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bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
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};
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char ARMLoadStoreOpt::ID = 0;
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}
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/// createARMLoadStoreOptimizationPass - returns an instance of the load / store
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/// optimization pass.
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FunctionPass *llvm::createARMLoadStoreOptimizationPass() {
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return new ARMLoadStoreOpt();
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}
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static int getLoadStoreMultipleOpcode(int Opcode) {
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switch (Opcode) {
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case ARM::LDR:
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NumLDMGened++;
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return ARM::LDM;
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case ARM::STR:
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NumSTMGened++;
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return ARM::STM;
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case ARM::FLDS:
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NumFLDMGened++;
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return ARM::FLDMS;
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case ARM::FSTS:
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NumFSTMGened++;
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return ARM::FSTMS;
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case ARM::FLDD:
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NumFLDMGened++;
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return ARM::FLDMD;
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case ARM::FSTD:
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NumFSTMGened++;
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return ARM::FSTMD;
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default: abort();
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}
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return 0;
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}
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/// mergeOps - Create and insert a LDM or STM with Base as base register and
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/// registers in Regs as the register operands that would be loaded / stored.
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/// It returns true if the transformation is done.
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static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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int Offset, unsigned Base, bool BaseKill, int Opcode,
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ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
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SmallVector<std::pair<unsigned, bool>, 8> &Regs,
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const TargetInstrInfo *TII) {
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// Only a single register to load / store. Don't bother.
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unsigned NumRegs = Regs.size();
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if (NumRegs <= 1)
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return false;
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ARM_AM::AMSubMode Mode = ARM_AM::ia;
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bool isAM4 = Opcode == ARM::LDR || Opcode == ARM::STR;
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if (isAM4 && Offset == 4)
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Mode = ARM_AM::ib;
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else if (isAM4 && Offset == -4 * (int)NumRegs + 4)
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Mode = ARM_AM::da;
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else if (isAM4 && Offset == -4 * (int)NumRegs)
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Mode = ARM_AM::db;
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else if (Offset != 0) {
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// If starting offset isn't zero, insert a MI to materialize a new base.
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// But only do so if it is cost effective, i.e. merging more than two
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// loads / stores.
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if (NumRegs <= 2)
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return false;
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unsigned NewBase;
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if (Opcode == ARM::LDR)
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// If it is a load, then just use one of the destination register to
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// use as the new base.
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NewBase = Regs[NumRegs-1].first;
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else {
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// Use the scratch register to use as a new base.
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NewBase = Scratch;
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if (NewBase == 0)
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return false;
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}
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int BaseOpc = ARM::ADDri;
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if (Offset < 0) {
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BaseOpc = ARM::SUBri;
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Offset = - Offset;
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}
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int ImmedOffset = ARM_AM::getSOImmVal(Offset);
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if (ImmedOffset == -1)
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return false; // Probably not worth it then.
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BuildMI(MBB, MBBI, TII->get(BaseOpc), NewBase)
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.addReg(Base, false, false, BaseKill).addImm(ImmedOffset)
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.addImm(Pred).addReg(PredReg).addReg(0);
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Base = NewBase;
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BaseKill = true; // New base is always killed right its use.
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}
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bool isDPR = Opcode == ARM::FLDD || Opcode == ARM::FSTD;
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bool isDef = Opcode == ARM::LDR || Opcode == ARM::FLDS || Opcode == ARM::FLDD;
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Opcode = getLoadStoreMultipleOpcode(Opcode);
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MachineInstrBuilder MIB = (isAM4)
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? BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill)
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.addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg)
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: BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill)
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.addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs))
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.addImm(Pred).addReg(PredReg);
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for (unsigned i = 0; i != NumRegs; ++i)
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MIB = MIB.addReg(Regs[i].first, isDef, false, Regs[i].second);
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return true;
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}
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/// MergeLDR_STR - Merge a number of load / store instructions into one or more
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/// load / store multiple instructions.
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SmallVector<MachineBasicBlock::iterator, 4>
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ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
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unsigned Base, int Opcode, unsigned Size,
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ARMCC::CondCodes Pred, unsigned PredReg,
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unsigned Scratch, MemOpQueue &MemOps) {
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SmallVector<MachineBasicBlock::iterator, 4> Merges;
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bool isAM4 = Opcode == ARM::LDR || Opcode == ARM::STR;
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int Offset = MemOps[SIndex].Offset;
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int SOffset = Offset;
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unsigned Pos = MemOps[SIndex].Position;
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MachineBasicBlock::iterator Loc = MemOps[SIndex].MBBI;
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unsigned PReg = MemOps[SIndex].MBBI->getOperand(0).getReg();
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unsigned PRegNum = ARMRegisterInfo::getRegisterNumbering(PReg);
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bool isKill = MemOps[SIndex].MBBI->getOperand(0).isKill();
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SmallVector<std::pair<unsigned,bool>, 8> Regs;
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Regs.push_back(std::make_pair(PReg, isKill));
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for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) {
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int NewOffset = MemOps[i].Offset;
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unsigned Reg = MemOps[i].MBBI->getOperand(0).getReg();
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unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
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isKill = MemOps[i].MBBI->getOperand(0).isKill();
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// AM4 - register numbers in ascending order.
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// AM5 - consecutive register numbers in ascending order.
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if (NewOffset == Offset + (int)Size &&
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((isAM4 && RegNum > PRegNum) || RegNum == PRegNum+1)) {
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Offset += Size;
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Regs.push_back(std::make_pair(Reg, isKill));
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PRegNum = RegNum;
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} else {
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// Can't merge this in. Try merge the earlier ones first.
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if (mergeOps(MBB, ++Loc, SOffset, Base, false, Opcode, Pred, PredReg,
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Scratch, Regs, TII)) {
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Merges.push_back(prior(Loc));
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for (unsigned j = SIndex; j < i; ++j) {
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MBB.erase(MemOps[j].MBBI);
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MemOps[j].Merged = true;
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}
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}
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SmallVector<MachineBasicBlock::iterator, 4> Merges2 =
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MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,MemOps);
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Merges.append(Merges2.begin(), Merges2.end());
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return Merges;
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}
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if (MemOps[i].Position > Pos) {
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Pos = MemOps[i].Position;
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Loc = MemOps[i].MBBI;
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}
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}
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bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1;
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if (mergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode, Pred, PredReg,
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Scratch, Regs, TII)) {
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Merges.push_back(prior(Loc));
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for (unsigned i = SIndex, e = MemOps.size(); i != e; ++i) {
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MBB.erase(MemOps[i].MBBI);
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MemOps[i].Merged = true;
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}
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}
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return Merges;
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}
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/// getInstrPredicate - If instruction is predicated, returns its predicate
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/// condition, otherwise returns AL. It also returns the condition code
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/// register by reference.
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static ARMCC::CondCodes getInstrPredicate(MachineInstr *MI, unsigned &PredReg) {
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int PIdx = MI->findFirstPredOperandIdx();
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if (PIdx == -1) {
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PredReg = 0;
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return ARMCC::AL;
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}
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PredReg = MI->getOperand(PIdx+1).getReg();
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return (ARMCC::CondCodes)MI->getOperand(PIdx).getImmedValue();
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}
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static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
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unsigned Bytes, ARMCC::CondCodes Pred,
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unsigned PredReg) {
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unsigned MyPredReg = 0;
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return (MI && MI->getOpcode() == ARM::SUBri &&
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MI->getOperand(0).getReg() == Base &&
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MI->getOperand(1).getReg() == Base &&
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ARM_AM::getAM2Offset(MI->getOperand(2).getImm()) == Bytes &&
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getInstrPredicate(MI, MyPredReg) == Pred &&
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MyPredReg == PredReg);
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}
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static inline bool isMatchingIncrement(MachineInstr *MI, unsigned Base,
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unsigned Bytes, ARMCC::CondCodes Pred,
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unsigned PredReg) {
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unsigned MyPredReg = 0;
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return (MI && MI->getOpcode() == ARM::ADDri &&
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MI->getOperand(0).getReg() == Base &&
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MI->getOperand(1).getReg() == Base &&
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ARM_AM::getAM2Offset(MI->getOperand(2).getImm()) == Bytes &&
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getInstrPredicate(MI, MyPredReg) == Pred &&
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MyPredReg == PredReg);
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}
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static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
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switch (MI->getOpcode()) {
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default: return 0;
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case ARM::LDR:
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case ARM::STR:
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case ARM::FLDS:
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case ARM::FSTS:
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return 4;
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case ARM::FLDD:
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case ARM::FSTD:
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return 8;
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case ARM::LDM:
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case ARM::STM:
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return (MI->getNumOperands() - 4) * 4;
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case ARM::FLDMS:
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case ARM::FSTMS:
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case ARM::FLDMD:
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case ARM::FSTMD:
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return ARM_AM::getAM5Offset(MI->getOperand(1).getImm()) * 4;
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}
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}
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/// mergeBaseUpdateLSMultiple - Fold proceeding/trailing inc/dec of base
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/// register into the LDM/STM/FLDM{D|S}/FSTM{D|S} op when possible:
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///
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/// stmia rn, <ra, rb, rc>
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/// rn := rn + 4 * 3;
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/// =>
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/// stmia rn!, <ra, rb, rc>
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///
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/// rn := rn - 4 * 3;
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/// ldmia rn, <ra, rb, rc>
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/// =>
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/// ldmdb rn!, <ra, rb, rc>
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static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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bool &Advance,
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MachineBasicBlock::iterator &I) {
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MachineInstr *MI = MBBI;
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unsigned Base = MI->getOperand(0).getReg();
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unsigned Bytes = getLSMultipleTransferSize(MI);
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
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int Opcode = MI->getOpcode();
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bool isAM4 = Opcode == ARM::LDM || Opcode == ARM::STM;
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if (isAM4) {
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if (ARM_AM::getAM4WBFlag(MI->getOperand(1).getImm()))
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return false;
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// Can't use the updating AM4 sub-mode if the base register is also a dest
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// register. e.g. ldmdb r0!, {r0, r1, r2}. The behavior is undefined.
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for (unsigned i = 3, e = MI->getNumOperands(); i != e; ++i) {
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if (MI->getOperand(i).getReg() == Base)
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return false;
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}
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ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm());
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if (MBBI != MBB.begin()) {
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MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
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if (Mode == ARM_AM::ia &&
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isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::db, true));
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MBB.erase(PrevMBBI);
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return true;
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} else if (Mode == ARM_AM::ib &&
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isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::da, true));
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MBB.erase(PrevMBBI);
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return true;
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}
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}
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if (MBBI != MBB.end()) {
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MachineBasicBlock::iterator NextMBBI = next(MBBI);
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if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) &&
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isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
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if (NextMBBI == I) {
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Advance = true;
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++I;
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}
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MBB.erase(NextMBBI);
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return true;
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} else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) &&
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isMatchingDecrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
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if (NextMBBI == I) {
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Advance = true;
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++I;
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}
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MBB.erase(NextMBBI);
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return true;
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}
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}
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} else {
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// FLDM{D|S}, FSTM{D|S} addressing mode 5 ops.
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if (ARM_AM::getAM5WBFlag(MI->getOperand(1).getImm()))
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return false;
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ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MI->getOperand(1).getImm());
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unsigned Offset = ARM_AM::getAM5Offset(MI->getOperand(1).getImm());
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if (MBBI != MBB.begin()) {
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MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
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if (Mode == ARM_AM::ia &&
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isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::db, true, Offset));
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MBB.erase(PrevMBBI);
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return true;
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}
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}
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if (MBBI != MBB.end()) {
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MachineBasicBlock::iterator NextMBBI = next(MBBI);
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if (Mode == ARM_AM::ia &&
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isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::ia, true, Offset));
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if (NextMBBI == I) {
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Advance = true;
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++I;
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}
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MBB.erase(NextMBBI);
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}
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return true;
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}
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}
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return false;
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}
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static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) {
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switch (Opc) {
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case ARM::LDR: return ARM::LDR_PRE;
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case ARM::STR: return ARM::STR_PRE;
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case ARM::FLDS: return ARM::FLDMS;
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case ARM::FLDD: return ARM::FLDMD;
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case ARM::FSTS: return ARM::FSTMS;
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case ARM::FSTD: return ARM::FSTMD;
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default: abort();
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}
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return 0;
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}
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static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) {
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switch (Opc) {
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case ARM::LDR: return ARM::LDR_POST;
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case ARM::STR: return ARM::STR_POST;
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case ARM::FLDS: return ARM::FLDMS;
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case ARM::FLDD: return ARM::FLDMD;
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case ARM::FSTS: return ARM::FSTMS;
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case ARM::FSTD: return ARM::FSTMD;
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default: abort();
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}
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return 0;
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}
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/// mergeBaseUpdateLoadStore - Fold proceeding/trailing inc/dec of base
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/// register into the LDR/STR/FLD{D|S}/FST{D|S} op when possible:
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static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const TargetInstrInfo *TII,
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bool &Advance,
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MachineBasicBlock::iterator &I) {
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MachineInstr *MI = MBBI;
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unsigned Base = MI->getOperand(1).getReg();
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bool BaseKill = MI->getOperand(1).isKill();
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unsigned Bytes = getLSMultipleTransferSize(MI);
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|
int Opcode = MI->getOpcode();
|
|
bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
|
|
if ((isAM2 && ARM_AM::getAM2Offset(MI->getOperand(3).getImm()) != 0) ||
|
|
(!isAM2 && ARM_AM::getAM5Offset(MI->getOperand(2).getImm()) != 0))
|
|
return false;
|
|
|
|
bool isLd = Opcode == ARM::LDR || Opcode == ARM::FLDS || Opcode == ARM::FLDD;
|
|
// Can't do the merge if the destination register is the same as the would-be
|
|
// writeback register.
|
|
if (isLd && MI->getOperand(0).getReg() == Base)
|
|
return false;
|
|
|
|
unsigned PredReg = 0;
|
|
ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
|
|
bool DoMerge = false;
|
|
ARM_AM::AddrOpc AddSub = ARM_AM::add;
|
|
unsigned NewOpc = 0;
|
|
if (MBBI != MBB.begin()) {
|
|
MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
|
|
if (isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg)) {
|
|
DoMerge = true;
|
|
AddSub = ARM_AM::sub;
|
|
NewOpc = getPreIndexedLoadStoreOpcode(Opcode);
|
|
} else if (isAM2 && isMatchingIncrement(PrevMBBI, Base, Bytes,
|
|
Pred, PredReg)) {
|
|
DoMerge = true;
|
|
NewOpc = getPreIndexedLoadStoreOpcode(Opcode);
|
|
}
|
|
if (DoMerge)
|
|
MBB.erase(PrevMBBI);
|
|
}
|
|
|
|
if (!DoMerge && MBBI != MBB.end()) {
|
|
MachineBasicBlock::iterator NextMBBI = next(MBBI);
|
|
if (isAM2 && isMatchingDecrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
|
|
DoMerge = true;
|
|
AddSub = ARM_AM::sub;
|
|
NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
|
|
} else if (isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
|
|
DoMerge = true;
|
|
NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
|
|
}
|
|
if (DoMerge) {
|
|
if (NextMBBI == I) {
|
|
Advance = true;
|
|
++I;
|
|
}
|
|
MBB.erase(NextMBBI);
|
|
}
|
|
}
|
|
|
|
if (!DoMerge)
|
|
return false;
|
|
|
|
bool isDPR = NewOpc == ARM::FLDMD || NewOpc == ARM::FSTMD;
|
|
unsigned Offset = isAM2 ? ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift)
|
|
: ARM_AM::getAM5Opc((AddSub == ARM_AM::sub) ? ARM_AM::db : ARM_AM::ia,
|
|
true, isDPR ? 2 : 1);
|
|
if (isLd) {
|
|
if (isAM2)
|
|
// LDR_PRE, LDR_POST;
|
|
BuildMI(MBB, MBBI, TII->get(NewOpc), MI->getOperand(0).getReg())
|
|
.addReg(Base, true)
|
|
.addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
|
|
else
|
|
// FLDMS, FLDMD
|
|
BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base, false, false, BaseKill)
|
|
.addImm(Offset).addImm(Pred).addReg(PredReg)
|
|
.addReg(MI->getOperand(0).getReg(), true);
|
|
} else {
|
|
MachineOperand &MO = MI->getOperand(0);
|
|
if (isAM2)
|
|
// STR_PRE, STR_POST;
|
|
BuildMI(MBB, MBBI, TII->get(NewOpc), Base)
|
|
.addReg(MO.getReg(), false, false, MO.isKill())
|
|
.addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
|
|
else
|
|
// FSTMS, FSTMD
|
|
BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base).addImm(Offset)
|
|
.addImm(Pred).addReg(PredReg)
|
|
.addReg(MO.getReg(), false, false, MO.isKill());
|
|
}
|
|
MBB.erase(MBBI);
|
|
|
|
return true;
|
|
}
|
|
|
|
/// isMemoryOp - Returns true if instruction is a memory operations (that this
|
|
/// pass is capable of operating on).
|
|
static bool isMemoryOp(MachineInstr *MI) {
|
|
int Opcode = MI->getOpcode();
|
|
switch (Opcode) {
|
|
default: break;
|
|
case ARM::LDR:
|
|
case ARM::STR:
|
|
return MI->getOperand(1).isRegister() && MI->getOperand(2).getReg() == 0;
|
|
case ARM::FLDS:
|
|
case ARM::FSTS:
|
|
return MI->getOperand(1).isRegister();
|
|
case ARM::FLDD:
|
|
case ARM::FSTD:
|
|
return MI->getOperand(1).isRegister();
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// AdvanceRS - Advance register scavenger to just before the earliest memory
|
|
/// op that is being merged.
|
|
void ARMLoadStoreOpt::AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps) {
|
|
MachineBasicBlock::iterator Loc = MemOps[0].MBBI;
|
|
unsigned Position = MemOps[0].Position;
|
|
for (unsigned i = 1, e = MemOps.size(); i != e; ++i) {
|
|
if (MemOps[i].Position < Position) {
|
|
Position = MemOps[i].Position;
|
|
Loc = MemOps[i].MBBI;
|
|
}
|
|
}
|
|
|
|
if (Loc != MBB.begin())
|
|
RS->forward(prior(Loc));
|
|
}
|
|
|
|
/// LoadStoreMultipleOpti - An optimization pass to turn multiple LDR / STR
|
|
/// ops of the same base and incrementing offset into LDM / STM ops.
|
|
bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
|
|
unsigned NumMerges = 0;
|
|
unsigned NumMemOps = 0;
|
|
MemOpQueue MemOps;
|
|
unsigned CurrBase = 0;
|
|
int CurrOpc = -1;
|
|
unsigned CurrSize = 0;
|
|
ARMCC::CondCodes CurrPred = ARMCC::AL;
|
|
unsigned CurrPredReg = 0;
|
|
unsigned Position = 0;
|
|
|
|
RS->enterBasicBlock(&MBB);
|
|
MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
|
|
while (MBBI != E) {
|
|
bool Advance = false;
|
|
bool TryMerge = false;
|
|
bool Clobber = false;
|
|
|
|
bool isMemOp = isMemoryOp(MBBI);
|
|
if (isMemOp) {
|
|
int Opcode = MBBI->getOpcode();
|
|
bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
|
|
unsigned Size = getLSMultipleTransferSize(MBBI);
|
|
unsigned Base = MBBI->getOperand(1).getReg();
|
|
unsigned PredReg = 0;
|
|
ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
|
|
const TargetInstrDescriptor *TID = MBBI->getInstrDescriptor();
|
|
unsigned OffField = MBBI->getOperand(TID->numOperands-3).getImm();
|
|
int Offset = isAM2
|
|
? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
|
|
if (isAM2) {
|
|
if (ARM_AM::getAM2Op(OffField) == ARM_AM::sub)
|
|
Offset = -Offset;
|
|
} else {
|
|
if (ARM_AM::getAM5Op(OffField) == ARM_AM::sub)
|
|
Offset = -Offset;
|
|
}
|
|
// Watch out for:
|
|
// r4 := ldr [r5]
|
|
// r5 := ldr [r5, #4]
|
|
// r6 := ldr [r5, #8]
|
|
//
|
|
// The second ldr has effectively broken the chain even though it
|
|
// looks like the later ldr(s) use the same base register. Try to
|
|
// merge the ldr's so far, including this one. But don't try to
|
|
// combine the following ldr(s).
|
|
Clobber = (Opcode == ARM::LDR && Base == MBBI->getOperand(0).getReg());
|
|
if (CurrBase == 0 && !Clobber) {
|
|
// Start of a new chain.
|
|
CurrBase = Base;
|
|
CurrOpc = Opcode;
|
|
CurrSize = Size;
|
|
CurrPred = Pred;
|
|
CurrPredReg = PredReg;
|
|
MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
|
|
NumMemOps++;
|
|
Advance = true;
|
|
} else {
|
|
if (Clobber) {
|
|
TryMerge = true;
|
|
Advance = true;
|
|
}
|
|
|
|
if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {
|
|
// No need to match PredReg.
|
|
// Continue adding to the queue.
|
|
if (Offset > MemOps.back().Offset) {
|
|
MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
|
|
NumMemOps++;
|
|
Advance = true;
|
|
} else {
|
|
for (MemOpQueueIter I = MemOps.begin(), E = MemOps.end();
|
|
I != E; ++I) {
|
|
if (Offset < I->Offset) {
|
|
MemOps.insert(I, MemOpQueueEntry(Offset, Position, MBBI));
|
|
NumMemOps++;
|
|
Advance = true;
|
|
break;
|
|
} else if (Offset == I->Offset) {
|
|
// Collision! This can't be merged!
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (Advance) {
|
|
++Position;
|
|
++MBBI;
|
|
} else
|
|
TryMerge = true;
|
|
|
|
if (TryMerge) {
|
|
if (NumMemOps > 1) {
|
|
// Try to find a free register to use as a new base in case it's needed.
|
|
// First advance to the instruction just before the start of the chain.
|
|
AdvanceRS(MBB, MemOps);
|
|
// Find a scratch register. Make sure it's a call clobbered register or
|
|
// a spilled callee-saved register.
|
|
unsigned Scratch = RS->FindUnusedReg(&ARM::GPRRegClass, true);
|
|
if (!Scratch)
|
|
Scratch = RS->FindUnusedReg(&ARM::GPRRegClass,
|
|
AFI->getSpilledCSRegisters());
|
|
// Process the load / store instructions.
|
|
RS->forward(prior(MBBI));
|
|
|
|
// Merge ops.
|
|
SmallVector<MachineBasicBlock::iterator,4> MBBII =
|
|
MergeLDR_STR(MBB, 0, CurrBase, CurrOpc, CurrSize,
|
|
CurrPred, CurrPredReg, Scratch, MemOps);
|
|
|
|
// Try folding preceeding/trailing base inc/dec into the generated
|
|
// LDM/STM ops.
|
|
for (unsigned i = 0, e = MBBII.size(); i < e; ++i)
|
|
if (mergeBaseUpdateLSMultiple(MBB, MBBII[i], Advance, MBBI))
|
|
NumMerges++;
|
|
NumMerges += MBBII.size();
|
|
|
|
// Try folding preceeding/trailing base inc/dec into those load/store
|
|
// that were not merged to form LDM/STM ops.
|
|
for (unsigned i = 0; i != NumMemOps; ++i)
|
|
if (!MemOps[i].Merged)
|
|
if (mergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII,Advance,MBBI))
|
|
NumMerges++;
|
|
|
|
// RS may be pointing to an instruction that's deleted.
|
|
RS->skipTo(prior(MBBI));
|
|
}
|
|
|
|
CurrBase = 0;
|
|
CurrOpc = -1;
|
|
CurrSize = 0;
|
|
CurrPred = ARMCC::AL;
|
|
CurrPredReg = 0;
|
|
if (NumMemOps) {
|
|
MemOps.clear();
|
|
NumMemOps = 0;
|
|
}
|
|
|
|
// If iterator hasn't been advanced and this is not a memory op, skip it.
|
|
// It can't start a new chain anyway.
|
|
if (!Advance && !isMemOp && MBBI != E) {
|
|
++Position;
|
|
++MBBI;
|
|
}
|
|
}
|
|
}
|
|
return NumMerges > 0;
|
|
}
|
|
|
|
/// MergeReturnIntoLDM - If this is a exit BB, try merging the return op
|
|
/// (bx lr) into the preceeding stack restore so it directly restore the value
|
|
/// of LR into pc.
|
|
/// ldmfd sp!, {r7, lr}
|
|
/// bx lr
|
|
/// =>
|
|
/// ldmfd sp!, {r7, pc}
|
|
bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
|
|
if (MBB.empty()) return false;
|
|
|
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
|
if (MBBI->getOpcode() == ARM::BX_RET && MBBI != MBB.begin()) {
|
|
MachineInstr *PrevMI = prior(MBBI);
|
|
if (PrevMI->getOpcode() == ARM::LDM) {
|
|
MachineOperand &MO = PrevMI->getOperand(PrevMI->getNumOperands()-1);
|
|
if (MO.getReg() == ARM::LR) {
|
|
PrevMI->setInstrDescriptor(TII->get(ARM::LDM_RET));
|
|
MO.setReg(ARM::PC);
|
|
MBB.erase(MBBI);
|
|
return true;
|
|
}
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
|
|
const TargetMachine &TM = Fn.getTarget();
|
|
AFI = Fn.getInfo<ARMFunctionInfo>();
|
|
TII = TM.getInstrInfo();
|
|
MRI = TM.getRegisterInfo();
|
|
RS = new RegScavenger();
|
|
|
|
bool Modified = false;
|
|
for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E;
|
|
++MFI) {
|
|
MachineBasicBlock &MBB = *MFI;
|
|
Modified |= LoadStoreMultipleOpti(MBB);
|
|
Modified |= MergeReturnIntoLDM(MBB);
|
|
}
|
|
|
|
delete RS;
|
|
return Modified;
|
|
}
|