mirror of
https://github.com/c64scene-ar/llvm-6502.git
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a032778dcf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227619 91177308-0d34-0410-b5e6-96231b3b80d8
210 lines
7.8 KiB
TableGen
210 lines
7.8 KiB
TableGen
//===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the Hexagon register file.
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//===----------------------------------------------------------------------===//
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let Namespace = "Hexagon" in {
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class HexagonReg<bits<5> num, string n, list<string> alt = [],
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list<Register> alias = []> : Register<n> {
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field bits<5> Num;
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let Aliases = alias;
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let HWEncoding{4-0} = num;
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}
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class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs,
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list<string> alt = []> :
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RegisterWithSubRegs<n, subregs> {
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field bits<5> Num;
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let AltNames = alt;
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let HWEncoding{4-0} = num;
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}
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// Registers are identified with 5-bit ID numbers.
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// Ri - 32-bit integer registers.
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class Ri<bits<5> num, string n, list<string> alt = []> : HexagonReg<num, n, alt> {
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let Num = num;
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}
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// Rf - 32-bit floating-point registers.
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class Rf<bits<5> num, string n> : HexagonReg<num, n> {
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let Num = num;
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}
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// Rd - 64-bit registers.
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class Rd<bits<5> num, string n, list<Register> subregs> :
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HexagonDoubleReg<num, n, subregs> {
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let Num = num;
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let SubRegs = subregs;
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}
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// Rp - predicate registers
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class Rp<bits<5> num, string n> : HexagonReg<num, n> {
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let Num = num;
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}
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// Rc - control registers
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class Rc<bits<5> num, string n,
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list<string> alt = [], list<Register> alias = []> :
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HexagonReg<num, n, alt, alias> {
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let Num = num;
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}
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// Rcc - 64-bit control registers.
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class Rcc<bits<5> num, string n, list<Register> subregs,
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list<string> alt = []> :
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HexagonDoubleReg<num, n, subregs, alt> {
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let Num = num;
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let SubRegs = subregs;
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}
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// Mx - address modifier registers
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class Mx<bits<1> num, string n> : HexagonReg<{0b0000, num}, n> {
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let Num = !cast<bits<5>>(num);
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}
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def subreg_loreg : SubRegIndex<32>;
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def subreg_hireg : SubRegIndex<32, 32>;
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def subreg_overflow : SubRegIndex<1, 0>;
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// Integer registers.
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foreach i = 0-28 in {
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def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>;
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}
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def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>;
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def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>;
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def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>;
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// Aliases of the R* registers used to hold 64-bit int values (doubles).
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let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
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def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
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def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
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def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
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def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
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def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
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def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
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def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>;
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def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
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def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>;
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def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>;
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def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>;
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def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>;
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def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>;
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def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>;
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def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>;
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def D15 : Rd<30, "r31:30", [R30, R31]>, DwarfRegNum<[62]>;
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}
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// Predicate registers.
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def P0 : Rp<0, "p0">, DwarfRegNum<[63]>;
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def P1 : Rp<1, "p1">, DwarfRegNum<[64]>;
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def P2 : Rp<2, "p2">, DwarfRegNum<[65]>;
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def P3 : Rp<3, "p3">, DwarfRegNum<[66]>;
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// Modifier registers.
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// C6 and C7 can also be M0 and M1, but register names must be unique, even
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// if belonging to different register classes.
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def M0 : Mx<0, "m0">, DwarfRegNum<[72]>;
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def M1 : Mx<1, "m1">, DwarfRegNum<[73]>;
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// Fake register to represent USR.OVF bit. Artihmetic/saturating instruc-
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// tions modify this bit, and multiple such instructions are allowed in the
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// same packet. We need to ignore output dependencies on this bit, but not
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// on the entire USR.
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def USR_OVF : Rc<?, "usr.ovf">;
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// Control registers.
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def SA0 : Rc<0, "sa0", ["c0"]>, DwarfRegNum<[67]>;
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def LC0 : Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>;
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def SA1 : Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>;
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def LC1 : Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>;
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def P3_0 : Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>,
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DwarfRegNum<[71]>;
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def C6 : Rc<6, "c6", [], [M0]>, DwarfRegNum<[72]>;
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def C7 : Rc<7, "c7", [], [M1]>, DwarfRegNum<[73]>;
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def USR : Rc<8, "usr", ["c8"]>, DwarfRegNum<[74]> {
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let SubRegIndices = [subreg_overflow];
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let SubRegs = [USR_OVF];
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}
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def PC : Rc<9, "pc">, DwarfRegNum<[75]>;
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def UGP : Rc<10, "ugp", ["c10"]>, DwarfRegNum<[76]>;
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def GP : Rc<11, "gp">, DwarfRegNum<[77]>;
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def CS0 : Rc<12, "cs0", ["c12"]>, DwarfRegNum<[78]>;
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def CS1 : Rc<13, "cs1", ["c13"]>, DwarfRegNum<[79]>;
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def UPCL : Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[80]>;
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def UPCH : Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[81]>;
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}
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// Control registers pairs.
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let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
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def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>;
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def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>;
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def C7_6 : Rcc<6, "c7:6", [C6, C7], ["m1:0"]>, DwarfRegNum<[72]>;
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def C9_8 : Rcc<8, "c9:8", [USR, PC]>, DwarfRegNum<[74]>;
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def C11_10 : Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>;
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def CS : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>;
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def UPC : Rcc<14, "c15:14", [UPCL, UPCH]>, DwarfRegNum<[80]>;
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}
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// Register classes.
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//
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// FIXME: the register order should be defined in terms of the preferred
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// allocation order...
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//
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def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32,
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(add (sequence "R%u", 0, 9),
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(sequence "R%u", 12, 28),
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R10, R11, R29, R30, R31)> {
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}
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def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64,
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(add (sequence "D%u", 0, 4),
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(sequence "D%u", 6, 13), D5, D14, D15)>;
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def PredRegs : RegisterClass<"Hexagon",
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[i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32,
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(add (sequence "P%u", 0, 3))>
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{
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let Size = 32;
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}
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let Size = 32 in
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def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>;
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let Size = 32, isAllocatable = 0 in
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def CtrRegs : RegisterClass<"Hexagon", [i32], 32,
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(add LC0, SA0, LC1, SA1,
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P3_0,
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M0, M1, C6, C7, CS0, CS1, UPCL, UPCH,
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USR, USR_OVF, UGP, GP, PC)>;
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let Size = 64, isAllocatable = 0 in
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def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64,
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(add C1_0, C3_2, C7_6, C9_8, C11_10, CS, UPC)>;
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def VolatileV3 {
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list<Register> Regs = [D0, D1, D2, D3, D4, D5, D6, D7,
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R28, R31,
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P0, P1, P2, P3,
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M0, M1,
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LC0, LC1, SA0, SA1, USR, USR_OVF];
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}
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def PositiveHalfWord : PatLeaf<(i32 IntRegs:$a),
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[{
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return isPositiveHalfWord(N);
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}]>;
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