mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-30 19:29:20 +00:00
fe5b65827f
For processors with the G5-like instruction-grouping scheme, this helps avoid early group termination due to a write-after-write dependency within the group. It should also help on pipelined embedded cores. On POWER7, over the test suite, this gives an average 0.5% speedup. The largest speedups are: SingleSource/Benchmarks/Stanford/Quicksort - 33% MultiSource/Applications/d/make_dparser - 21% MultiSource/Benchmarks/FreeBench/analyzer/analyzer - 12% MultiSource/Benchmarks/MiBench/telecomm-FFT/telecomm-fft - 12% Largest slowdowns: SingleSource/Benchmarks/Stanford/Bubblesort - 23% MultiSource/Benchmarks/Prolangs-C++/city/city - 21% MultiSource/Benchmarks/BitBench/uuencode/uuencode - 16% MultiSource/Benchmarks/mediabench/mpeg2/mpeg2dec/mpeg2decode - 13% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158719 91177308-0d34-0410-b5e6-96231b3b80d8
82 lines
2.8 KiB
C++
82 lines
2.8 KiB
C++
//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the PowerPC implementation of the TargetRegisterInfo
|
|
// class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef POWERPC32_REGISTERINFO_H
|
|
#define POWERPC32_REGISTERINFO_H
|
|
|
|
#include "PPC.h"
|
|
#include <map>
|
|
|
|
#define GET_REGINFO_HEADER
|
|
#include "PPCGenRegisterInfo.inc"
|
|
|
|
namespace llvm {
|
|
class PPCSubtarget;
|
|
class TargetInstrInfo;
|
|
class Type;
|
|
|
|
class PPCRegisterInfo : public PPCGenRegisterInfo {
|
|
std::map<unsigned, unsigned> ImmToIdxMap;
|
|
const PPCSubtarget &Subtarget;
|
|
const TargetInstrInfo &TII;
|
|
public:
|
|
PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);
|
|
|
|
/// getPointerRegClass - Return the register class to use to hold pointers.
|
|
/// This is used for addressing modes.
|
|
virtual const TargetRegisterClass *
|
|
getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const;
|
|
|
|
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
|
|
MachineFunction &MF) const;
|
|
|
|
/// Code Generation virtual methods...
|
|
const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
|
|
const unsigned *getCallPreservedMask(CallingConv::ID CC) const;
|
|
|
|
BitVector getReservedRegs(const MachineFunction &MF) const;
|
|
|
|
virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
|
|
|
|
/// requiresRegisterScavenging - We require a register scavenger.
|
|
/// FIXME (64-bit): Should be inlined.
|
|
bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
|
|
|
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
|
|
|
|
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
|
MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const;
|
|
|
|
void lowerDynamicAlloc(MachineBasicBlock::iterator II,
|
|
int SPAdj, RegScavenger *RS) const;
|
|
void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex,
|
|
int SPAdj, RegScavenger *RS) const;
|
|
void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex,
|
|
int SPAdj, RegScavenger *RS) const;
|
|
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
int SPAdj, RegScavenger *RS = NULL) const;
|
|
|
|
// Debug information queries.
|
|
unsigned getFrameRegister(const MachineFunction &MF) const;
|
|
|
|
// Exception handling queries.
|
|
unsigned getEHExceptionRegister() const;
|
|
unsigned getEHHandlerRegister() const;
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|