mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-27 13:30:05 +00:00
ba61446a56
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206877 91177308-0d34-0410-b5e6-96231b3b80d8
345 lines
12 KiB
LLVM
345 lines
12 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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; arm64 has (the non-trivial parts of) this test covered by vcmp.ll
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;; Scalar Integer Compare
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define i64 @test_vceqd(i64 %a, i64 %b) {
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; CHECK: test_vceqd
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; CHECK: cmeq {{d[0-9]+}}, {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vceq.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vceq1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vceq2.i = call <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1i64.v1i64(<1 x i64> %vceq.i, <1 x i64> %vceq1.i)
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%0 = extractelement <1 x i64> %vceq2.i, i32 0
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ret i64 %0
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}
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define i64 @test_vceqzd(i64 %a) {
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; CHECK: test_vceqzd
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; CHECK: cmeq {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vceqz.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vceqz1.i = call <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1i64.v1i64(<1 x i64> %vceqz.i, <1 x i64> zeroinitializer)
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%0 = extractelement <1 x i64> %vceqz1.i, i32 0
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ret i64 %0
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}
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define i64 @test_vcged(i64 %a, i64 %b) {
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; CHECK: test_vcged
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; CHECK: cmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcge.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcge1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1i64.v1i64(<1 x i64> %vcge.i, <1 x i64> %vcge1.i)
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%0 = extractelement <1 x i64> %vcge2.i, i32 0
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ret i64 %0
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}
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define i64 @test_vcgezd(i64 %a) {
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; CHECK: test_vcgezd
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; CHECK: cmge {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vcgez.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcgez1.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1i64.v1i64(<1 x i64> %vcgez.i, <1 x i64> zeroinitializer)
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%0 = extractelement <1 x i64> %vcgez1.i, i32 0
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ret i64 %0
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}
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define i64 @test_vcgtd(i64 %a, i64 %b) {
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; CHECK: test_vcgtd
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; CHECK: cmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcgt.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcgt1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1i64.v1i64(<1 x i64> %vcgt.i, <1 x i64> %vcgt1.i)
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%0 = extractelement <1 x i64> %vcgt2.i, i32 0
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ret i64 %0
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}
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define i64 @test_vcgtzd(i64 %a) {
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; CHECK: test_vcgtzd
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; CHECK: cmgt {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vcgtz.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcgtz1.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1i64.v1i64(<1 x i64> %vcgtz.i, <1 x i64> zeroinitializer)
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%0 = extractelement <1 x i64> %vcgtz1.i, i32 0
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ret i64 %0
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}
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define i64 @test_vcled(i64 %a, i64 %b) {
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; CHECK: test_vcled
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; CHECK: cmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcgt.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vcgt1.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1i64.v1i64(<1 x i64> %vcgt.i, <1 x i64> %vcgt1.i)
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%0 = extractelement <1 x i64> %vcgt2.i, i32 0
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ret i64 %0
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}
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define i64 @test_vclezd(i64 %a) {
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; CHECK: test_vclezd
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; CHECK: cmle {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vclez.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vclez1.i = call <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1i64.v1i64(<1 x i64> %vclez.i, <1 x i64> zeroinitializer)
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%0 = extractelement <1 x i64> %vclez1.i, i32 0
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ret i64 %0
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}
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define i64 @test_vcltd(i64 %a, i64 %b) {
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; CHECK: test_vcltd
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; CHECK: cmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcge.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vcge1.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1i64.v1i64(<1 x i64> %vcge.i, <1 x i64> %vcge1.i)
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%0 = extractelement <1 x i64> %vcge2.i, i32 0
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ret i64 %0
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}
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define i64 @test_vcltzd(i64 %a) {
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; CHECK: test_vcltzd
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; CHECK: cmlt {{d[0-9]}}, {{d[0-9]}}, #0x0
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entry:
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%vcltz.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vcltz1.i = call <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1i64.v1i64(<1 x i64> %vcltz.i, <1 x i64> zeroinitializer)
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%0 = extractelement <1 x i64> %vcltz1.i, i32 0
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ret i64 %0
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}
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define i64 @test_vtstd(i64 %a, i64 %b) {
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; CHECK: test_vtstd
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; CHECK: cmtst {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vtst.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%vtst1.i = insertelement <1 x i64> undef, i64 %b, i32 0
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%vtst2.i = call <1 x i64> @llvm.aarch64.neon.vtstd.v1i64.v1i64.v1i64(<1 x i64> %vtst.i, <1 x i64> %vtst1.i)
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%0 = extractelement <1 x i64> %vtst2.i, i32 0
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ret i64 %0
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}
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define <1 x i64> @test_vcage_f64(<1 x double> %a, <1 x double> %b) #0 {
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; CHECK: test_vcage_f64
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; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%vcage2.i = tail call <1 x i64> @llvm.arm.neon.vacge.v1i64.v1f64(<1 x double> %a, <1 x double> %b) #2
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ret <1 x i64> %vcage2.i
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}
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define <1 x i64> @test_vcagt_f64(<1 x double> %a, <1 x double> %b) #0 {
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; CHECK: test_vcagt_f64
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; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%vcagt2.i = tail call <1 x i64> @llvm.arm.neon.vacgt.v1i64.v1f64(<1 x double> %a, <1 x double> %b) #2
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ret <1 x i64> %vcagt2.i
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}
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define <1 x i64> @test_vcale_f64(<1 x double> %a, <1 x double> %b) #0 {
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; CHECK: test_vcale_f64
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; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%vcage2.i = tail call <1 x i64> @llvm.arm.neon.vacge.v1i64.v1f64(<1 x double> %b, <1 x double> %a) #2
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ret <1 x i64> %vcage2.i
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}
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define <1 x i64> @test_vcalt_f64(<1 x double> %a, <1 x double> %b) #0 {
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; CHECK: test_vcalt_f64
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; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%vcagt2.i = tail call <1 x i64> @llvm.arm.neon.vacgt.v1i64.v1f64(<1 x double> %b, <1 x double> %a) #2
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ret <1 x i64> %vcagt2.i
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}
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define <1 x i64> @test_vceq_s64(<1 x i64> %a, <1 x i64> %b) #0 {
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; CHECK: test_vceq_s64
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; CHECK: cmeq {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = icmp eq <1 x i64> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vceq_u64(<1 x i64> %a, <1 x i64> %b) #0 {
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; CHECK: test_vceq_u64
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; CHECK: cmeq {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = icmp eq <1 x i64> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vceq_f64(<1 x double> %a, <1 x double> %b) #0 {
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; CHECK: test_vceq_f64
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; CHECK: fcmeq {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = fcmp oeq <1 x double> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vcge_s64(<1 x i64> %a, <1 x i64> %b) #0 {
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; CHECK: test_vcge_s64
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; CHECK: cmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = icmp sge <1 x i64> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vcge_u64(<1 x i64> %a, <1 x i64> %b) #0 {
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; CHECK: test_vcge_u64
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; CHECK: cmhs {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = icmp uge <1 x i64> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vcge_f64(<1 x double> %a, <1 x double> %b) #0 {
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; CHECK: test_vcge_f64
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; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = fcmp oge <1 x double> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vcle_s64(<1 x i64> %a, <1 x i64> %b) #0 {
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; CHECK: test_vcle_s64
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; CHECK: cmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = icmp sle <1 x i64> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vcle_u64(<1 x i64> %a, <1 x i64> %b) #0 {
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; CHECK: test_vcle_u64
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; CHECK: cmhs {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = icmp ule <1 x i64> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vcle_f64(<1 x double> %a, <1 x double> %b) #0 {
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; CHECK: test_vcle_f64
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; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = fcmp ole <1 x double> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vcgt_s64(<1 x i64> %a, <1 x i64> %b) #0 {
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; CHECK: test_vcgt_s64
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; CHECK: cmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = icmp sgt <1 x i64> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vcgt_u64(<1 x i64> %a, <1 x i64> %b) #0 {
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; CHECK: test_vcgt_u64
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; CHECK: cmhi {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = icmp ugt <1 x i64> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vcgt_f64(<1 x double> %a, <1 x double> %b) #0 {
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; CHECK: test_vcgt_f64
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; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = fcmp ogt <1 x double> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vclt_s64(<1 x i64> %a, <1 x i64> %b) #0 {
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; CHECK: test_vclt_s64
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; CHECK: cmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = icmp slt <1 x i64> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vclt_u64(<1 x i64> %a, <1 x i64> %b) #0 {
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; CHECK: test_vclt_u64
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; CHECK: cmhi {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = icmp ult <1 x i64> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vclt_f64(<1 x double> %a, <1 x double> %b) #0 {
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; CHECK: test_vclt_f64
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; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
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%cmp.i = fcmp olt <1 x double> %a, %b
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%sext.i = sext <1 x i1> %cmp.i to <1 x i64>
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ret <1 x i64> %sext.i
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}
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define <1 x i64> @test_vceqz_s64(<1 x i64> %a) #0 {
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; CHECK: test_vceqz_s64
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; CHECK: cmeq {{d[0-9]}}, {{d[0-9]}}, #0x0
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%1 = icmp eq <1 x i64> %a, zeroinitializer
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%vceqz.i = sext <1 x i1> %1 to <1 x i64>
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ret <1 x i64> %vceqz.i
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}
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define <1 x i64> @test_vceqz_u64(<1 x i64> %a) #0 {
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; CHECK: test_vceqz_u64
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; CHECK: cmeq {{d[0-9]}}, {{d[0-9]}}, #0x0
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%1 = icmp eq <1 x i64> %a, zeroinitializer
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%vceqz.i = sext <1 x i1> %1 to <1 x i64>
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ret <1 x i64> %vceqz.i
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}
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define <1 x i64> @test_vceqz_p64(<1 x i64> %a) #0 {
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; CHECK: test_vceqz_p64
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; CHECK: cmeq {{d[0-9]}}, {{d[0-9]}}, #0x0
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%1 = icmp eq <1 x i64> %a, zeroinitializer
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%vceqz.i = sext <1 x i1> %1 to <1 x i64>
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ret <1 x i64> %vceqz.i
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}
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define <2 x i64> @test_vceqzq_p64(<2 x i64> %a) #0 {
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; CHECK: test_vceqzq_p64
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; CHECK: cmeq {{v[0-9]}}.2d, {{v[0-9]}}.2d, #0
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%1 = icmp eq <2 x i64> %a, zeroinitializer
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%vceqz.i = sext <2 x i1> %1 to <2 x i64>
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ret <2 x i64> %vceqz.i
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}
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define <1 x i64> @test_vcgez_s64(<1 x i64> %a) #0 {
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; CHECK: test_vcgez_s64
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; CHECK: cmge {{d[0-9]}}, {{d[0-9]}}, #0x0
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%1 = icmp sge <1 x i64> %a, zeroinitializer
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%vcgez.i = sext <1 x i1> %1 to <1 x i64>
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ret <1 x i64> %vcgez.i
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}
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define <1 x i64> @test_vclez_s64(<1 x i64> %a) #0 {
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; CHECK: test_vclez_s64
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; CHECK: cmle {{d[0-9]}}, {{d[0-9]}}, #0x0
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%1 = icmp sle <1 x i64> %a, zeroinitializer
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%vclez.i = sext <1 x i1> %1 to <1 x i64>
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ret <1 x i64> %vclez.i
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}
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define <1 x i64> @test_vcgtz_s64(<1 x i64> %a) #0 {
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; CHECK: test_vcgtz_s64
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; CHECK: cmgt {{d[0-9]}}, {{d[0-9]}}, #0x0
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%1 = icmp sgt <1 x i64> %a, zeroinitializer
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%vcgtz.i = sext <1 x i1> %1 to <1 x i64>
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ret <1 x i64> %vcgtz.i
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}
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|
|
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define <1 x i64> @test_vcltz_s64(<1 x i64> %a) #0 {
|
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; CHECK: test_vcltz_s64
|
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; CHECK: cmlt {{d[0-9]}}, {{d[0-9]}}, #0
|
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%1 = icmp slt <1 x i64> %a, zeroinitializer
|
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%vcltz.i = sext <1 x i1> %1 to <1 x i64>
|
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ret <1 x i64> %vcltz.i
|
|
}
|
|
|
|
declare <1 x i64> @llvm.arm.neon.vacgt.v1i64.v1f64(<1 x double>, <1 x double>)
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|
declare <1 x i64> @llvm.arm.neon.vacge.v1i64.v1f64(<1 x double>, <1 x double>)
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|
declare <1 x i64> @llvm.aarch64.neon.vtstd.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
|
declare <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
|
declare <1 x i64> @llvm.aarch64.neon.vchs.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
|
declare <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
|
declare <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
|
declare <1 x i64> @llvm.aarch64.neon.vchi.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
|
declare <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|
|
declare <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>)
|