Elena Demikhovsky 1cec507d6d AVX-512: changes in intrinsics ... 1) Changed gather and scatter intrinsics. Now they are aligned with GCC built-ins. There is no more non-masked form. Masked intrinsic receives -1 if all lanes are executed. 2) I changed the function that works with intrinsics inside X86ISelLowering.cpp. I put all intrinsics in one table. I did it for INTRINSICS_W_CHAIN and plan to put all intrinsics from WO_CHAIN set to the same table in order to avoid the long-long "switch". (I wanted to use static map initialization that allowed by C++11 but I wasn't able to compile it on VS2012). 3) I added gather/scatter prefetch intrinsics. 4) I fixed MRMm encoding for masked instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208522 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-12 07:18:51 +00:00
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AArch64	AArch64/ARM64: optimise vector selects & enable test	2014-05-07 14:10:27 +00:00
ARM	Fix ARM intrinsics-overflow.ll test on Windows	2014-05-09 21:52:48 +00:00
ARM64	ARM64: fix SELECT_CC lowering in absence of NaNs.	2014-05-10 07:37:50 +00:00
CPP
Generic	MC: move test from Generic to COFF	2014-04-23 21:41:07 +00:00
Hexagon
Inputs
Mips	Allow sret on the second parameter as well as the first	2014-05-09 22:32:13 +00:00
MSP430
NVPTX	Fix the test: DCE optimized away everything.	2014-04-21 17:23:12 +00:00
PowerPC	[PowerPC] Add global named register support	2014-05-11 19:29:11 +00:00
R600	R600/SI: Fold fabs/fneg into src input modifier	2014-05-10 19:18:39 +00:00
SPARC	Allow sret on the second parameter as well as the first	2014-05-09 22:32:13 +00:00
SystemZ
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X86	AVX-512: changes in intrinsics	2014-05-12 07:18:51 +00:00
XCore	Reapply "blockfreq: Rewrite BlockFrequencyInfoImpl"	2014-04-21 17:57:07 +00:00