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https://github.com/c64scene-ar/llvm-6502.git
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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
158 lines
7.3 KiB
C++
158 lines
7.3 KiB
C++
//===-- ARM64InstPrinter.h - Convert ARM64 MCInst to assembly syntax ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an ARM64 MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARM64INSTPRINTER_H
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#define ARM64INSTPRINTER_H
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#include "MCTargetDesc/ARM64MCTargetDesc.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCInstPrinter.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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namespace llvm {
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class MCOperand;
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class ARM64InstPrinter : public MCInstPrinter {
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public:
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ARM64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
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virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
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virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
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// Autogenerated by tblgen.
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virtual void printInstruction(const MCInst *MI, raw_ostream &O);
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virtual bool printAliasInstr(const MCInst *MI, raw_ostream &O);
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virtual StringRef getRegName(unsigned RegNo) const {
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return getRegisterName(RegNo);
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}
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static const char *getRegisterName(unsigned RegNo,
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unsigned AltIdx = ARM64::NoRegAltName);
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protected:
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bool printSysAlias(const MCInst *MI, raw_ostream &O);
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// Operand printers
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void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
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raw_ostream &O);
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void printPostIncOperand1(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPostIncOperand2(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPostIncOperand3(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPostIncOperand4(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPostIncOperand6(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPostIncOperand8(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPostIncOperand12(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPostIncOperand16(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPostIncOperand24(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPostIncOperand32(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPostIncOperand48(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPostIncOperand64(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printVRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printSysCROperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printAddSubImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printLogicalImm32(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printLogicalImm64(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printShifter(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printShiftedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printExtendedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printDotCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printAlignedBranchTarget(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printAMIndexed(const MCInst *MI, unsigned OpNum, unsigned Scale,
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raw_ostream &O);
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void printAMIndexed128(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printAMIndexed(MI, OpNum, 16, O);
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}
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void printAMIndexed64(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printAMIndexed(MI, OpNum, 8, O);
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}
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void printAMIndexed32(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printAMIndexed(MI, OpNum, 4, O);
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}
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void printAMIndexed16(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printAMIndexed(MI, OpNum, 2, O);
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}
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void printAMIndexed8(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printAMIndexed(MI, OpNum, 1, O);
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}
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void printAMUnscaled(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
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printAMIndexed(MI, OpNum, 1, O);
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}
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void printAMNoIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printImmScale4(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printImmScale8(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printImmScale16(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printPrefetchOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMemoryPostIndexed(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMemoryPostIndexed32(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printMemoryPostIndexed64(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printMemoryPostIndexed128(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printMemoryRegOffset(const MCInst *MI, unsigned OpNum, raw_ostream &O,
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int LegalShiftAmt);
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void printMemoryRegOffset8(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMemoryRegOffset16(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMemoryRegOffset32(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMemoryRegOffset64(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMemoryRegOffset128(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O,
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StringRef LayoutSuffix);
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/// Print a list of vector registers where the type suffix is implicit
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/// (i.e. attached to the instruction rather than the registers).
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void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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template <unsigned NumLanes, char LaneKind>
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void printTypedVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printVectorIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printAdrpLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printBarrierOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printSystemRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printSystemCPSRField(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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};
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class ARM64AppleInstPrinter : public ARM64InstPrinter {
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public:
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ARM64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
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virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
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virtual void printInstruction(const MCInst *MI, raw_ostream &O);
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virtual bool printAliasInstr(const MCInst *MI, raw_ostream &O);
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virtual StringRef getRegName(unsigned RegNo) const {
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return getRegisterName(RegNo);
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}
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static const char *getRegisterName(unsigned RegNo,
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unsigned AltIdx = ARM64::NoRegAltName);
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};
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}
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#endif
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