Jakob Stoklund Olesen 7ae14f3d97 Add a scheduling model for Intel Sandy Bridge microarchitecture. ... The model isn't hooked up by this patch because the instruction set isn't fully annotated yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177942 91177308-0d34-0410-b5e6-96231b3b80d8		2013-03-25 23:37:17 +00:00
..
Analysis	Support in AAEvaluator to print alias queries of loads/stores with TBAA tags.	2013-03-22 22:34:41 +00:00
Archive
AsmParser
Bitcode
CodeGen	Disable some unsafe-fp-math DAG-combine transformation after legalization.	2013-03-25 22:52:29 +00:00
DebugInfo	Fix missing std::. Not sure how this compiles for anyone else.	2013-03-21 00:57:21 +00:00
ExecutionEngine
IR	Swap the DIFile in DILexicalBlockFile out for the raw name/directory pair	2013-03-22 20:18:46 +00:00
Linker	The Linker interface has some dead code after the cleanup in r172749	2013-03-19 15:26:24 +00:00
MC	Dead code.	2013-03-19 22:13:05 +00:00
Object
Option
Support	Revert r177543: Add timing of the IR parsing code with a new	2013-03-22 02:20:34 +00:00
TableGen	Allow TableGen DAG arguments to be just a name.	2013-03-24 19:36:51 +00:00
Target	Add a scheduling model for Intel Sandy Bridge microarchitecture.	2013-03-25 23:37:17 +00:00
Transforms	Fix a bug in fast-math fadd/fsub simplification.	2013-03-25 20:43:41 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile