llvm-6502/test/MC/Disassembler
Bob Wilson cfbece50f6 ARM instructions that are both predicated and set the condition codes
have been printed with the "S" modifier after the predicate.  With ARM's
unified syntax, they are supposed to go in the other order.  We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM.  Apparently we don't generate these instructions often because no one
noticed until now.  Thanks to Bill Wendling for the testcase!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15 03:23:44 +00:00
..
arm-tests.txt ARM instructions that are both predicated and set the condition codes 2010-10-15 03:23:44 +00:00
dg.exp
neon-tests.txt
simple-tests.txt Added a testcase for the ENTER instruction. 2010-10-05 00:21:40 +00:00
thumb-tests.txt