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https://github.com/c64scene-ar/llvm-6502.git
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2da8bc8a5f
DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
121 lines
3.8 KiB
C++
121 lines
3.8 KiB
C++
//===-- ARMHazardRecognizer.cpp - ARM postra hazard recognizer ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMHazardRecognizer.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
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const TargetRegisterInfo &TRI) {
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// FIXME: Detect integer instructions properly.
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const TargetInstrDesc &TID = MI->getDesc();
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unsigned Domain = TID.TSFlags & ARMII::DomainMask;
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if (Domain == ARMII::DomainVFP) {
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unsigned Opcode = MI->getOpcode();
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if (Opcode == ARM::VSTRS || Opcode == ARM::VSTRD ||
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Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
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return false;
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} else if (Domain == ARMII::DomainNEON) {
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if (MI->getDesc().mayStore() || MI->getDesc().mayLoad())
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return false;
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} else
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return false;
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return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
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}
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ScheduleHazardRecognizer::HazardType
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ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
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assert(Stalls == 0 && "ARM hazards don't support scoreboard lookahead");
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MachineInstr *MI = SU->getInstr();
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if (!MI->isDebugValue()) {
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if (ITBlockSize && MI != ITBlockMIs[ITBlockSize-1])
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return Hazard;
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// Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
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// a VMLA / VMLS will cause 4 cycle stall.
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const TargetInstrDesc &TID = MI->getDesc();
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if (LastMI && (TID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
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MachineInstr *DefMI = LastMI;
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const TargetInstrDesc &LastTID = LastMI->getDesc();
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// Skip over one non-VFP / NEON instruction.
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if (!LastTID.isBarrier() &&
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(LastTID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
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MachineBasicBlock::iterator I = LastMI;
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if (I != LastMI->getParent()->begin()) {
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I = llvm::prior(I);
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DefMI = &*I;
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}
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}
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if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
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(TII.canCauseFpMLxStall(MI->getOpcode()) ||
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hasRAWHazard(DefMI, MI, TRI))) {
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// Try to schedule another instruction for the next 4 cycles.
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if (FpMLxStalls == 0)
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FpMLxStalls = 4;
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return Hazard;
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}
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}
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}
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return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
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}
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void ARMHazardRecognizer::Reset() {
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LastMI = 0;
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FpMLxStalls = 0;
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ITBlockSize = 0;
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ScoreboardHazardRecognizer::Reset();
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}
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void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
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MachineInstr *MI = SU->getInstr();
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unsigned Opcode = MI->getOpcode();
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if (ITBlockSize) {
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--ITBlockSize;
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} else if (Opcode == ARM::t2IT) {
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unsigned Mask = MI->getOperand(1).getImm();
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unsigned NumTZ = CountTrailingZeros_32(Mask);
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assert(NumTZ <= 3 && "Invalid IT mask!");
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ITBlockSize = 4 - NumTZ;
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MachineBasicBlock::iterator I = MI;
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for (unsigned i = 0; i < ITBlockSize; ++i) {
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// Advance to the next instruction, skipping any dbg_value instructions.
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do {
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++I;
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} while (I->isDebugValue());
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ITBlockMIs[ITBlockSize-1-i] = &*I;
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}
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}
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if (!MI->isDebugValue()) {
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LastMI = MI;
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FpMLxStalls = 0;
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}
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ScoreboardHazardRecognizer::EmitInstruction(SU);
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}
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void ARMHazardRecognizer::AdvanceCycle() {
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if (FpMLxStalls && --FpMLxStalls == 0)
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// Stalled for 4 cycles but still can't schedule any other instructions.
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LastMI = 0;
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ScoreboardHazardRecognizer::AdvanceCycle();
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}
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void ARMHazardRecognizer::RecedeCycle() {
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llvm_unreachable("reverse ARM hazard checking unsupported");
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}
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