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Make addPassesToEmitAssembly() look slightly more like addPassesToJITCompile(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10818 91177308-0d34-0410-b5e6-96231b3b80d8
242 lines
8.6 KiB
C++
242 lines
8.6 KiB
C++
//===-- Sparc.cpp - General implementation file for the Sparc Target ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Primary interface to machine description for the UltraSPARC. Primarily just
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// initializes machine-dependent parameters in class TargetMachine, and creates
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// machine-dependent subclasses for classes such as TargetInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Function.h"
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#include "llvm/IntrinsicLowering.h"
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#include "llvm/PassManager.h"
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#include "llvm/Assembly/PrintModulePass.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetMachineImpls.h"
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#include "llvm/Transforms/Scalar.h"
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#include "MappingInfo.h"
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#include "SparcInternals.h"
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#include "SparcTargetMachine.h"
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#include "Support/CommandLine.h"
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using namespace llvm;
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static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
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// Build the MachineInstruction Description Array...
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const TargetInstrDescriptor llvm::SparcMachineInstrDesc[] = {
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#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
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{ OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0, \
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ImplicitRegUseList, ImplicitRegUseList },
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#include "SparcInstr.def"
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};
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//---------------------------------------------------------------------------
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// Command line options to control choice of code generation passes.
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//---------------------------------------------------------------------------
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namespace {
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cl::opt<bool> DisableSched("disable-sched",
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cl::desc("Disable local scheduling pass"));
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cl::opt<bool> DisablePeephole("disable-peephole",
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cl::desc("Disable peephole optimization pass"));
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cl::opt<bool> EmitMappingInfo("enable-maps",
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cl::desc("Emit LLVM-to-MachineCode mapping info to assembly"));
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cl::opt<bool> DisableStrip("disable-strip",
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cl::desc("Do not strip the LLVM bytecode in executable"));
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}
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//===---------------------------------------------------------------------===//
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// Code generation/destruction passes
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//===---------------------------------------------------------------------===//
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namespace {
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class ConstructMachineFunction : public FunctionPass {
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TargetMachine &Target;
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public:
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ConstructMachineFunction(TargetMachine &T) : Target(T) {}
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const char *getPassName() const {
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return "ConstructMachineFunction";
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}
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bool runOnFunction(Function &F) {
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MachineFunction::construct(&F, Target).getInfo()->CalculateArgSize();
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return false;
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}
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};
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struct DestroyMachineFunction : public FunctionPass {
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const char *getPassName() const { return "FreeMachineFunction"; }
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static void freeMachineCode(Instruction &I) {
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MachineCodeForInstruction::destroy(&I);
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}
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bool runOnFunction(Function &F) {
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for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
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for (BasicBlock::iterator I = FI->begin(), E = FI->end(); I != E; ++I)
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MachineCodeForInstruction::get(I).dropAllReferences();
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for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
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for_each(FI->begin(), FI->end(), freeMachineCode);
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MachineFunction::destruct(&F);
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return false;
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}
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};
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FunctionPass *createMachineCodeConstructionPass(TargetMachine &Target) {
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return new ConstructMachineFunction(Target);
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}
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}
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FunctionPass *llvm::createSparcMachineCodeDestructionPass() {
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return new DestroyMachineFunction();
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}
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SparcTargetMachine::SparcTargetMachine(IntrinsicLowering *il)
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: TargetMachine("UltraSparc-Native", il, false),
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schedInfo(*this),
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regInfo(*this),
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frameInfo(*this),
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cacheInfo(*this),
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jitInfo(*this) {
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}
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// addPassesToEmitAssembly - This method controls the entire code generation
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// process for the ultra sparc.
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//
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bool
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SparcTargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
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{
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// The following 3 passes used to be inserted specially by llc.
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// Replace malloc and free instructions with library calls.
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PM.add(createLowerAllocationsPass());
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// Strip all of the symbols from the bytecode so that it will be smaller...
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if (!DisableStrip)
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PM.add(createSymbolStrippingPass());
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// FIXME: implement the switch instruction in the instruction selector.
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PM.add(createLowerSwitchPass());
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// FIXME: implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// decompose multi-dimensional array references into single-dim refs
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PM.add(createDecomposeMultiDimRefsPass());
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// Construct and initialize the MachineFunction object for this fn.
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PM.add(createMachineCodeConstructionPass(*this));
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//Insert empty stackslots in the stack frame of each function
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//so %fp+offset-8 and %fp+offset-16 are empty slots now!
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PM.add(createStackSlotsPass(*this));
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// Specialize LLVM code for this target machine and then
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// run basic dataflow optimizations on LLVM code.
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PM.add(createPreSelectionPass(*this));
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PM.add(createReassociatePass());
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PM.add(createLICMPass());
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PM.add(createGCSEPass());
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PM.add(createInstructionSelectionPass(*this));
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if (!DisableSched)
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PM.add(createInstructionSchedulingWithSSAPass(*this));
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PM.add(getRegisterAllocator(*this));
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PM.add(createPrologEpilogInsertionPass());
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if (!DisablePeephole)
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PM.add(createPeepholeOptsPass(*this));
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if (EmitMappingInfo)
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PM.add(getMappingInfoAsmPrinterPass(Out));
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// Output assembly language to the .s file. Assembly emission is split into
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// two parts: Function output and Global value output. This is because
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// function output is pipelined with all of the rest of code generation stuff,
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// allowing machine code representations for functions to be free'd after the
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// function has been emitted.
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//
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PM.add(createAsmPrinterPass(Out, *this));
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PM.add(createSparcMachineCodeDestructionPass()); // Free mem no longer needed
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// Emit bytecode to the assembly file into its special section next
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if (EmitMappingInfo)
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PM.add(createBytecodeAsmPrinterPass(Out));
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return false;
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}
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// addPassesToJITCompile - This method controls the JIT method of code
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// generation for the UltraSparc.
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//
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void SparcJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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const TargetData &TD = TM.getTargetData();
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PM.add(new TargetData("lli", TD.isLittleEndian(), TD.getPointerSize(),
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TD.getPointerAlignment(), TD.getDoubleAlignment()));
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// Replace malloc and free instructions with library calls.
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// Do this after tracing until lli implements these lib calls.
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// For now, it will emulate malloc and free internally.
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PM.add(createLowerAllocationsPass());
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// FIXME: implement the switch instruction in the instruction selector.
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PM.add(createLowerSwitchPass());
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// FIXME: implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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// decompose multi-dimensional array references into single-dim refs
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PM.add(createDecomposeMultiDimRefsPass());
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// Construct and initialize the MachineFunction object for this fn.
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PM.add(createMachineCodeConstructionPass(TM));
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// Specialize LLVM code for this target machine and then
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// run basic dataflow optimizations on LLVM code.
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PM.add(createPreSelectionPass(TM));
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PM.add(createReassociatePass());
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// FIXME: these passes crash the FunctionPassManager when being added...
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//PM.add(createLICMPass());
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//PM.add(createGCSEPass());
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PM.add(createInstructionSelectionPass(TM));
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PM.add(getRegisterAllocator(TM));
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PM.add(createPrologEpilogInsertionPass());
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if (!DisablePeephole)
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PM.add(createPeepholeOptsPass(TM));
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}
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//----------------------------------------------------------------------------
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// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
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// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
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//----------------------------------------------------------------------------
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TargetMachine *llvm::allocateSparcTargetMachine(const Module &M,
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IntrinsicLowering *IL) {
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return new SparcTargetMachine(IL);
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}
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